LTC3851A_15 Datasheet, PDF (20/30 Pages) Linear Technology – Synchronous Step-Down Switching Regulator Controller

LTC3851A
Applications Information
The loop filter components, C_LP and R_LP, smooth out
the current pulses from the phase detector and provide
a stable input to the voltage-controlled oscillator. The
filter components C_LP and R_LP determine how fast the
loop acquires lock. Typically R_LP is 1k to 10k and C_LP is
2200pF to 0.01μF.
When the external oscillator is active before the LTC3851A
is enabled, the internal oscillator frequency will track the
external oscillator frequency as described in the preceding
paragraphs. In situations where the LTC3851A is enabled
before the external oscillator is active, a low free-running
oscillator frequency of approximately 50kHz will result. It is
possible to increase the free-running, pre-synchronization
frequency by adding a second resistor, R_FREQ, in parallel
with R_LP and C_LP. R_FREQ will also cause a phase difference
between the internal and external oscillator signals. The
magnitude of the phase difference is inversely proportional
to the value of R_FREQ. The free-running frequency may be
programmed by using Figure 7 to determine the appropri-
ate value of R_FREQ. In order to maintain adequate phase
margin for the PLL, the typical value for C_LP is 0.01µF
and for R_LP is 1k.
The external clock (on MODE/PLLIN pin) input high
threshold is nominally 1.6V, while the input low thres­hold
is nominally 1.2V.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time dura-
tion that the LTC3851A is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
t_ON(MIN)
<
V_OUT
V_IN(f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3851A is approximately
90ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases. This is of particu­
lar concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent­
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3851A circuits: 1) IC V_IN current, 2) INTV_CC
regulator current, 3) I²R losses, 4) topside MOSFET
transition losses.
1. The V_IN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver current. V_IN current typi­cally results in a small
(<0.1%) loss.
2. INTV_CC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTV_CC to ground. The resulting dQ/dt is a cur­rent
out of INTV_CC that is typically much larger than the
control circuit current. In continuous mode, I_GATECHG
= f(Q_T + Q_B), where Q_T and Q_B are the gate charges of
the topside and bottom side MOSFETs.
3851afa
20