LTC3850-1_15 Datasheet, PDF (12/38 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down Switching Controller

LTC3850/LTC3850-1
OPERATION
When a controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though
the voltage on the I_TH pin indicates a lower value. If the
average inductor current is higher than the load current,
the error amplifier EA will decrease the voltage on the I_TH
pin. When the I_TH voltage drops below 0.5V, the internal
sleep signal goes high (enabling “sleep” mode) and both
external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator
(I_REV) turns off the bottom external MOSFET just before the
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor current
is determined by the voltage on the I_TH pin, just as in nor-
mal operation. In this mode, the efficiency at light loads is
lower than in Burst Mode operation. However, continuous
mode has the advantages of lower output ripple and less
interference with audio circuitry.
When the MODE/PLLIN pin is connected to INTV_CC,
the LTC3850 operates in PWM pulse-skipping mode at
light loads. At very light loads, the current comparator
I_CMP may remain tripped for several cycles and force the
external top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output ripple
as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
low current efficiency than forced continuous mode, but
not nearly as high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage. The switching frequency
of the LTC3850’s controllers can be selected using the
FREQ/PLLFLTR pin. If the MODE/PLLIN pin is not being
driven by an external clock source, the FREQ/PLLFLTR
pin can be used to program the controller’s operating
frequency from 250kHz to 780kHz.
A phase-locked loop (PLL) is available on the LTC3850
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller is operating in forced continuous mode when
it is synchronized. A series R-C should be connected
between the FREQ/PLLFLTR pin and SGND to serve as
the PLL’s loop filter.
Power Good (PGOOD Pin)
The PGOOD pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when either V_FB pin voltage is not within
±7.5% of the 0.8V reference voltage. The PGOOD pin is
also pulled low when either RUN pin is below 1.2V or when
the LTC3850 is in the soft-start or tracking phase. When
the V_FB pin voltage is within the ±7.5% requirement, the
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 6V. The
PGOOD pin will flag power good immediately when both
V_FB pins are within the ±7.5% window. However, there is
an internal 17µs power bad mask when either V_FB goes
out of the ±7.5% window.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (> 7.5%) as well as other more serious con-
ditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
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