LTM4641 Datasheet, PDF (31/64 Pages) Linear Technology – 38V, 10A DC/DC Module Regulator with Advanced Input and Load Protection

LTM4641
APPLICATIONS INFORMATION—INPUT PROTECTION FEATURES
R_TOV’s value in place often significantly alters one or both
V_IN referred overvoltage thresholds. It is more efficient to
work through Equations 24 to 27 in the sequence shown
and iterate (if necessary) towards finding convenient (EIA
standard) resistor values.
The latchoff input overvoltage threshold can be double-
checked with:
V_OV
= UVOV_TH
•


R_TOV +R_MOV
R_BOV
+ 1^{}
(28)
The nonlatching overvoltage threshold can be double-
checked with:
( ) ^
V_RT = UVOV_TH • _
R_TOV
R_MOV +R_BOV

+ 1_
(29)
The UVLO, IOVRETRY and OVLO pins do not require any
filter capacitance due to built-in filtering in the LTM4641’s
housekeeping IC. This results in glitch immunity with
characteristics shown in Figure 12.
700
600
RESPECTIVE
500
FAULT CONDITION
BECOMES DETECTED
400
300
200
100
GLITCH
0 ^IGNORED
0.1
1
10
100
COMPARATOR OVERDRIVE PAST THRESHOLD (%)
4641 F12
Figure 12. Transient Duration vs Comparator Overdrive
Glitch Immunity Characteristics. Monitored Signals: UVLO,
IOVRETRY, OVLO, TEMP, CROWBAR and DRV_CC
Start-Up/Shutdown and Run Enable; Power-On Reset
and Timeout Delay Time
The LTM4641 is a feature-rich and versatile self-contained
DC/DC converter system, and includes multiple on-board
supply monitors. The inputs to several monitors are avail-
able to the user for system customization (UVLO, OVLO,
IOVRETRY and TEMP).
The LTM4641 powers up its output when the following
conditions are met:
• RUN exceeds 1.25V (nominal; 2V, overtemperature);
power-on reset (POR) and timeout delay times do not
apply to RUN.
• All nonlatching fault-monitor pins have been in their
operationally valid states for the full duration of the
POR delay time, set optionally by C_TMR (the capacitor
on the TMR pin). Explicit pins and operationally valid
thresholds follow:
a. DRV_CC > 4.05V. In the circuits of Figures 45 and
46, this is guaranteed for V_INL ≥ 4.5V, minimum. In
Figure 49, this requirement is met when the auxiliary
bias supply exceeds 4.05V.
b. UVLO > 500mV
c. IOVRETRY < 500mV
d. TEMP > 514mV (when OTBH is electrically open
circuit)
• No latchoff fault conditions are present, and the LTM4641
is not in a “latched off” state from any previously detected
latchoff fault condition. If a latchoff fault condition oc-
curs/occurred, the LTM4641 must be unlatched by a logic
high LATCH signal: if all latchoff fault-monitoring pins are
in operationally valid states when LATCH transitions from
logic low to high, the LTM4641 becomes immediately
unlatched; if, instead, any latchoff fault-monitoring pin
is outside its operationally valid state when LATCH is
logic high, the LTM4641 becomes unlatched if LATCH
remains logic high after all latchoff fault-monitoring
pins have been in their operationally valid states for the
full duration of the timeout delay time (set optionally by
C_TMR). Explicit pins and operationally valid thresholds
follow:
a. OVLO < 500mV
b. TEMP > 514mV (when OTBH is logic low)
c. CROWBAR < 1.5V
The POR and timeout delay time is 9ms per nanofarad
of C_TMR capacitance. If C_TMR is not used, the POR and
timeout delay time is ~90μs.
4641f
31