LTM4641 Datasheet, PDF (11/64 Pages) Linear Technology – 38V, 10A DC/DC Module Regulator with Advanced Input and Load Protection

LTM4641
PIN FUNCTIONS
CROWBAR (B9): Crowbar Output Pin. Normally logic low,
with moderate pull-down strength to SGND.
When an output overvoltage (OOV) condition is detected,
the LTM4641’s fast OOV comparator pulls CROWBAR logic
high through a series-connected internal diode. If utilizing
LTM4641’s OOV feature, CROWBAR should connect to
the gate of a logic-level N-channel MOSFET configured to
crowbar the module’s output voltage (MCB, in Figure 1).
Furthermore, the LTM4641 latches off its output when
CROWBAR nominally exceeds 1.5V and latches HYST
logic low (see HYST).
If not using the OOV protection features of the LTM4641,
leave CROWBAR electrically open circuit.
OV_PGM (B10): Output Overvoltage Threshold Programming
Pin. The voltage on this pin sets the trip threshold for the
inverting input pin of LTM4641’s fast OOV comparator.
When left electrically open circuit, resistors internal to the
LTM4641 nominally bias OV_PGM to 666mV (OV_PTH)—11%
above the nominal V_FB feedback voltage (600mV) that the
control loop strives to present to the noninverting input pin
of LTM4641’s fast OOV comparator. The aforementioned
voltages correspond proportionally to the module’s OOV
inception threshold and V_OUT’s nominal voltage of regula-
tion, respectively. Altering the OV_PGM voltage provides a
means to adjust the OOV threshold; its DC-bias setpoint
can be tightened with simple connections to external
components (see the Applications Information section).
Trace route lengths and widths to this sensitive analog
node should be minimized. Minimize stray capacitance to
this node unless altering the OOV threshold as described
in the Applications Information section and Appendix F.
LATCH (C5): Latchoff Reset Pin. When a latchoff fault oc-
curs, the LTM4641 turns off its output and latches M_HYST
on to indicate a fault condition has occurred (see HYST). To
configure the LTM4641 for latched off response to latchoff
faults, connect LATCH to SGND. As long as LATCH is logic
low, the LTM4641 will not unlatch. Regulation can be re-
sumed by cycling V_INL or by toggling LATCH from logic low
to high. It is also permissible to connect LATCH to INTV_CC;
this configures the LTM4641 for autonomous restart with a
timeout delay (programmed by C_TMR—see TMR).
If no latchoff faults are present when LATCH transitions
from logic low to logic high, the LTM4641 immediately un-
latches. If any latchoff fault is present when LATCH is logic
high, a timeout delay timing requirement is imposed: the
LTM4641 will not unlatch until all latchoff fault-monitoring
pins meet operationally valid states for the full duration
of the timeout delay. If LATCH becomes logic low before
that timeout delay has expired, the LTM4641 remains
latched off and the timeout delay is reset. Unlatching the
LTM4641 can be reattempted by pulling LATCH logic high
at a later time.
The following are latchoff fault conditions:
• CROWBAR activates (see CROWBAR)
• Input latchoff overvoltage fault (see OVLO)
• Latchoff overtemperature fault (when OTBH is logic
low; see TEMP and OTBH)
LATCH is a high impedance input and must not be left elec-
trically open circuit. LATCH can be driven by a μController
in intelligent systems: a reasonable implementation for
unlatching the LTM4641 is to pull LATCH logic high for
the maximum anticipated timeout delay time—after which,
HYST can be observed to indicate whether the LTM4641
has become unlatched.
1V_REF (C6): Buffered 1V Reference Output Pin. Minimize
capacitance on this pin, to assure the OV_PGM and TEMP
pins are operational in a timely manner at power-up. 1V_REF
should never be externally loaded except as explained in
the Applications Information section.
V_OUT (C9-C12; D9-D12; E9-E12): Power Output Pins of
the LTM4641 DC/DC Converter Power Stage. All V_OUT pins
are electrically connected to each other, internally. Apply
output load between these pins and the GND pins. It is
recommended to place output decoupling capacitance
directly between these pins and the GND pins. Review
Table 9. See the Layout Checklist/Example section of the
Applications Information section.
V_ORB+ (D1): V_OSNS+ Readback Pin. This pin connects to
V_OSNS+ internal to the µModule regulator. It is recommended
to route this pin (differentially with V_ORB–) to a test point
so as to allow the user a way to confirm the integrity of
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