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LTC3780_12 Datasheet, PDF (23/28 Pages) Linear Technology – High Effi ciency, Synchronous, 4-Switch Buck-Boost Controller | |||
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LTC3780
APPLICATIONS INFORMATION
Double-check the TJ in the MOSFET with 70°C ambient
temperature:
TJ = 70°C + 1.94W ⢠40°C/W = 147.6°C
The maximum power dissipation of switch B occurs in
buck mode. Assuming a junction temperature of TJ = 80°C
with Ï80°C = 1.2, the power dissipation at VIN = 18V is:
PB,BUCK
=
18 â 12
18
â¢
52
â¢
1.2
â¢
0.009
=
90mW
Double-check the TJ in the MOSFET at 70°C ambient
temperature:
TJ = 70°C + 0.09W ⢠40°C/W = 73.6°C
The maximum power dissipation of switch C occurs in boost
mode. Assuming a junction temperature of TJ = 110°C with
Ï110°C = 1.4, the power dissipation at VIN = 5V is:
PC,BOOST
=
(12
â 5)
52
⢠12
â¢
52
⢠1.4
â¢
0.009
+ 2 â¢123 ⢠5 â¢150p ⢠400k = 1.27W
5
Double-check the TJ in the MOSFET at 70°C ambient
temperature:
TJ = 70°C + 1.08W ⢠40°C/W = 113°C
The maximum power dissipation of switch D occurs
in boost mode when its duty cycle is higher than 50%.
Assuming a junction temperature of TJ = 100°C with
Ï100°C = 1.35, the power dissipation at VIN = 5V is:
PD,BOOST
=
5
12
s
â
ââ
12
5
s
5ââ â
2
s
135
s
0009
=
073W
Double-check the TJ in the MOSFET at 70°C ambient
temperature:
TJ = 70°C + 0.73W ⢠40°C/W = 99°C
CIN is chosen to ï¬lter the square current in buck mode. In
this mode, the maximum input current peak is:
IIN,PEAK(MAX,BUCK)
=
5
s
â
ââ
1+
29%
2
â
â â
=
5.7A
A low ESR (10mΩ) capacitor is selected. Input voltage
ripple is 57mV (assuming ESR dominate ripple).
COUT is chosen to ï¬lter the square current in boost mode.
In this mode, the maximum output current peak is:
IOUT,PEAK(MAX,BOOST)
=
12
5
s
5
s
â
ââ
1+
11%
2
â
â â
=
10.6A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 53mV (assuming ESR
dominate ripple).
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
⢠The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
⢠Place CIN, switch A, switch B and D1 in one com-
pact area. Place COUT, switch C, switch D and D2 in
one compact area. One layout example is shown in
Figure 10.
VIN
QA
CIN
SW2
SW1
L
D1
QB
QC
VOUT
D2
QD
COUT
RSENSE
LTC3780
CKT
Figure 10. Switches Layout
GND
3780 F10
3780fe
23
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