LTC3780_12 Datasheet, PDF (10/28 Pages) Linear Technology – High Effi ciency, Synchronous, 4-Switch Buck-Boost Controller

LTC3780
PIN FUNCTIONS (SSOP/QFN)
V_OSENSE (Pin 6/Pin 4): Error Amplifier Feedback Input.
This pin connects the error amplifier input to an external
resistor divider from V_OUT.
SGND (Pin 7/Pin 5): Signal Ground. All small-signal com-
ponents and compensation components should connect
to this ground, which should be connected to PGND at a
single point.
RUN (Pin 8/Pin 6): Run Control Input. Forcing the RUN
pin below 1.5V causes the IC to shut down the switching
regulator circuitry. There is a 100k resistor between the RUN
pin and SGND in the IC. Do not apply >6V to this pin.
FCB (Pin 9/Pin 7): Forced Continuous Control Input. The
voltage applied to this pin sets the operating mode of the
controller. When the applied voltage is less than 0.8V, the
forced continuous current mode is active. When this pin
is allowed to float, the Burst Mode operation is active in
boost operation and the skip-cycle mode is active in buck
operation. When the pin is tied to INTV_CC, the constant
frequency discontinuous current mode is active in buck
or boost operation.
PLLFLTR (Pin 10/Pin 8): The phase-locked loop’s
lowpass filter is tied to this pin. Alternatively, this pin can
be driven with an AC or DC voltage source to vary the
frequency of the internal oscillator.
PLLIN (Pin 11/Pin 10): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50kΩ. The phase-locked loop will force the rising
bottom gate signal of the controller to be synchronized
with the rising edge of the PLLIN signal.
STBYMD (Pin 12/Pin 11): LDO Control Pin. Determines
whether the internal LDO remains active when the control-
ler is shut down. See Operation section for details. If the
STBYMD pin is pulled to ground, the SS pin is internally
pulled to ground, preventing start-up and thereby provid-
ing a single control pin for turning off the controller. To
keep the LDO active when RUN is low, for example to
power a “wake up” circuit which controls the state of the
RUN pin, bypass STBYMD to signal ground with a 0.1μF
capacitor, or use a resistor divider from V_IN to keep the
pin within 2V to 5V.
BOOST2, BOOST1 (Pins 13, 24/Pins 14, 27): Boosted
Floating Driver Supply. The (+) terminal of the bootstrap
capacitor C_A and C_B (Figure 11) connects here. The BOOST2
pin swings from a diode voltage below INTV_CC up to V_IN
+ INTV_CC. The BOOST1 pin swings from a diode voltage
below INTV_CC up to V_OUT + INTV_CC.
TG2, TG1 (Pins 14, 23/Pins 15, 26): Top Gate Drive. Drives
the top N-channel MOSFET with a voltage swing equal to
INTV_CC superimposed on the switch node voltage SW.
SW2, SW1 (Pins 15, 22/Pins 17, 24): Switch Node. The (–)
terminal of the bootstrap capacitor C_A and C_B (Figure 11)
connects here. The SW2 pin swings from a Schottky diode
(external) voltage drop below ground up to V_IN. The SW1
pin swings from a Schottky diode (external) voltage drop
below ground up to V_OUT.
BG2, BG1 (Pins 16, 18/Pins 18, 20): Bottom Gate Drive.
Drives the gate of the bottom N-channel MOSFET between
ground and INTV_CC.
PGND (Pin 17/Pin 19): Power Ground. Connect this pin
closely to the source of the bottom N-channel MOSFET, the
(–) terminal of C_VCC and the (–) terminal of C_IN (Figure 11).
INTV_CC (Pin 19/Pin 21): Internal 6V Regulator Output. The
driver and control circuits are powered from this voltage.
Bypass this pin to ground with a minimum of 4.7μF low
ESR tantalum or ceramic capacitor.
EXTV_CC (Pin 20/Pin 22): External V_CC Input. When EXTV_CC
exceeds 5.7V, an internal switch connects this pin to INTV_CC
and shuts down the internal regulator so that the controller
and gate drive power is drawn from EXTV_CC. Do not exceed
7V at this pin and ensure that EXTV_CC < V_IN.
V_IN (Pin 21/Pin 23): Main Input Supply. Bypass this pin
to SGND with an RC filter (1Ω, 0.1μF).
Exposed Pad (Pin 33, QFN Only): This pin is SGND and
must be soldered to PCB ground.
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