LTC4010 Datasheet, PDF (18/20 Pages) Linear Integrated Systems – High Efficiency Standalone Nickel Battery Charger

LTC4010
APPLICATIO S I FOR ATIO
PCB Layout Considerations
To prevent magnetic and electrical field radiation and high
frequency resonant problems, proper layout of the com-
ponents connected to the LTC4010 is essential. Refer to
Figure 12. For maximum efficiency, the switch node rise
and fall times should be minimized. The following PCB
design priority list will help ensure proper topology. Lay-
out the PCB using this specific order.
1. Input capacitors should be placed as close as possible
to switching FET supply and ground connections with
the shortest copper traces possible. The switching
FETs must be on the same layer of copper as the input
capacitors. Vias should not be used to make these
connections.
2. Place the LTC4010 close to the switching FET gate
terminals, keeping the connecting traces short to
produce clean drive signals. This rule also applies to
IC supply and ground pins that connect to the switch-
ing FET source pins. The IC can be placed on the
opposite side of the PCB from the switching FETs.
3. Place the inductor input as close as possible to the
drain of the switching FETs. Minimize the surface area
of the switch node. Make the trace width the minimum
needed to support the programmed charge current.
Use no copper fills or pours. Avoid running the con-
nection on multiple copper layers in parallel. Minimize
capacitance from the switch node to any other trace or
plane.
4. Place the charge current sense resistor immediately
adjacent to the inductor output, and orient it such that
current sense traces to the LTC4010 are not long.
These feedback traces need to be run together as a
single pair with the smallest spacing possible on any
given layer on which they are routed. Locate any filter
component on these traces next to the LTC4010, and
not at the sense resistor location.
5. Place output capacitors next to the sense resisitor
output and ground.
6. Output capacitor ground connections must feed into
the same copper that connects to the input capacitor
ground before tying back into system ground.
7. Connection of switching ground to system ground, or
any internal ground plane should be single-point. If
the system has an internal system ground plane, a
good way to do this is to cluster vias into a single star
point to make the connection.
8. Route analog ground as a trace tied back to the
LTC4010 GND pin before connecting to any other
ground. Avoid using the system ground plane. A
useful CAD technique is to make analog ground a
separate ground net and use a 0Ω resistor to connect
analog ground to system ground.
9. A good rule of thumb for via count in a given high
current path is to use 0.5A per via. Be consistent when
applying this rule.
10. If possible, place all the parts listed above on the same
PCB layer.
11. Copper fills or pours are good for all power connec-
tions except as noted above in Rule 3. Copper planes
on multiple layers can also be used in parallel. This
helps with thermal management and lowers trace
inductance, which further improves EMI performance.
12. For best current programming accuracy, provide a
Kelvin connection from R_SENSE to SENSE and BAT.
See Figure 13 for an example.
13. It is important to minimize parasitic capacitance on
the TIMER, SENSE and BAT pins. The traces connect-
ing these pins to their respective resistors should be
as short as possible.
4010p
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