ISPLSI2128V Datasheet, PDF (9/15 Pages) Lattice Semiconductor – 3.3V High Density Programmable Logic

Specifications ispLSI 2128V
Pin Description
NAME
160-PIN PQFP PIN NUMBERS 176-PIN TQFP PIN NUMBERS
DESCRIPTION
I/O 0 - I/O 4
I/O 5 - I/O 9
I/O 10 - I/O 14
25, 26, 27, 28, 29,
30, 31, 32, 33, 34,
35, 36, 37, 38, 40,
28, 29, 30, 31, 32,
33, 34, 35, 37, 38,
39, 40, 41, 42, 44,
Input/Output Pins - These are the general
purpose I/O pins used by the logic array.
I/O 15 - I/O 19
41, 43, 44, 45, 46,
45, 47, 48, 49, 50,
I/O 20 - I/O 24
47, 48, 49, 50, 51,
51, 52, 53, 54, 56,
I/O 25 - I/O 29
52, 53, 54, 55, 56,
57, 58, 59, 60, 61,
I/O 30 - I/O 34
I/O 35 - I/O 39
I/O 40 - I/O 44
I/O 45 - I/O 49
I/O 50 - I/O 54
I/O 55 - I/O 59
I/O 60 - I/O 64
I/O 65 - I/O 69
I/O 70 - I/O 74
I/O 75 - I/O 79
I/O 80 - I/O 84
I/O 85 - I/O 89
I/O 90 - I/O 94
I/O 95 - I/O 99
I/O 100 - I/O 104
57, 58, 63, 64, 65,
66, 67, 68, 69, 70,
71, 72, 73, 74, 75,
76, 77, 78, 80, 81,
83, 84, 85, 86, 87,
88, 89, 90, 91, 92,
93, 94, 95, 96, 105,
106, 107, 108, 109, 110,
111, 112, 113, 114, 115,
116, 117, 118, 120, 121,
123, 124, 125, 126, 127,
128, 129, 130, 131, 132,
133, 134, 135, 136, 137,
138, 143, 144, 145, 146,
147, 148, 149, 150, 151,
62, 63, 70, 71, 72,
73, 74, 75, 76, 77,
79, 80, 81, 82, 83,
84, 85, 86, 88, 89,
91, 92, 93, 94, 95,
96, 98, 99, 100, 101,
102, 103, 104, 105, 116,
117, 118, 119, 120, 121,
122, 123, 125, 126, 127,
128, 129, 130, 132, 133,
135, 136, 137, 138, 139,
140, 141, 142, 144, 145,
146, 147, 148, 149, 150,
151, 158, 159, 160, 161,
162, 163, 164, 165, 167,
DESIGNS
I/O 105 - I/O 109
152, 153, 154, 155, 156,
168, 169, 170, 171, 172,
I/O 110 - I/O 114
I/O 115 - I/O 119
I/O 120 - I/O 124
I/O 125 - I/O 127
IN 4 - IN 7
GOE 0, GOE 1
RESET
Y0, Y1, Y2
157, 158, 160, 1, 3,
4, 5, 6, 7, 8,
9, 10, 11, 12, 13,
14, 15, 16
104, 141, 61, 17
100, 21
19
18, 103, 98
173,
4,
10,
15,
114,
110,
21
20,
174, 176, 1, 3,
5, 6, 7, 8,
11, 12, 13, 14,
W _{16, 17}
E _{155, 67, 19}
N ₂₃
FOR ^{113, 108}
Dedicated input pins to the device
Global Output Enable input pins
Active Low (0) Reset pin which resets all
the registers in the device.
Dedicated Clock input. This clock input is
connected to one of the clock inputs of
all the GLBs in the device.
ispEN
TDI/IN 0
TCK/IN 3
TMS/IN 1
23
25
8VE 24
26
212 97
107
ispLSI ⁶⁰
66
TDO/IN 2
USE ^GND
140
22, 42, 62, 79, 99,
122, 139, 159
154
24, 46, 68, 87, 109,
134, 153, 175
Input Dedicated in-system programming
Boundary Scan enable input pin. This pin is
brought low to enable the programming
mode. The TMS, TDI, TDO and TCK
controls become active.
Input This pin performs two functions.
When ispEN is logic low, it functions as a
serial data input pin to load programming
data into the device. When ispEN is high,
it functions as a dedicated input pin.
Input This pin performs two functions.
When ispEN is logic low, it functions as a
clock pin for the ISP/Boundary Scan state
machine.When ispEN is high, it functions as
a dedicated input pin.
Input This pin performs two functions.
When ispEN is logic low, it functions as a
mode control pin for the ISP/Boundary Scan
state machine. When ispEN is high, it
functions as a dedicated input pin.
Output/Input This pin performs two
functions. When ispEN is logic low, it
functions as an output pin to read serial
shift register data. When ispEN is high, it
functions as a dedicated input pin.
Ground (GND)
VCC
2,
20, 39, 59, 82,
101, 119, 142
2,
22, 43, 65, 90,
Vcc
111, 131, 156
NC¹
102
9, 18, 27, 36, 55,
64, 69, 78, 97, 106,
112, 115, 124, 143, 152,
157, 166
No Connect.
1. NC pins are not to be connected to any active signal, VCC or GND.
Table 2-0002A/2128V
9