ISPLSI2128V Datasheet, PDF (1/15 Pages) Lattice Semiconductor – 3.3V High Density Programmable Logic

ispLSI^® 2128V
3.3V High Density Programmable Logic
Features
Functional Block Diagram*
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
Output Routing Pool (ORP)
Output Routing Pool (ORP)
— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
D7 D6 D5 D4 D3 D2 D1 D0
— 128 Registers
— High Speed Global Interconnect
A0
— Wide Input Gating for Fast Counters, State
A1
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
A2
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE
A3
— Interfaces with Standard 5V TTL Devices
— The 128 I/O Pin Version is Fuse Map Compatible
A4
with 5V ispLSI 2128
A5
• HIGH PERFORMANCE E²CMOS^® TECHNOLOGY
— fmax = 80 MHz Maximum Operating Frequency
A6
C7
C6
S _{D Q}
C5
N_C4
DQ
IG _Logic
Array
DQ
GLB
C3
S _C2
ED Q
D ^C1
— tpd = 10 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
A7
Global Routing Pool (GRP)
B0
B1 B2 B3
W _{Output Routing Pool (ORP)}
B4 B5 B6 B7
Output Routing Pool (ORP)
NE ^{*128 I/O Version Shown}
C0
0139A/2128V
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
R _{Boundary Scan Test Access Port (TAP)}
O ^{— Open-Drain Output Option for Flexible Bus Interface}
Capability, Allowing Easy Implementation of
F _{Wired-OR or Bus Arbitration Logic}
— Increased Manufacturing Yields, Reduced Time-to-
E _{Market and Improved Product Quality}
— Reprogram Soldered Devices for Faster Prototyping
8V • THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
2 _{— Enhanced Pin Locking Capability}
1 _{— Three Dedicated Clock Input Pins}
2 _{— Synchronous and Asynchronous Clocks}
I _{— Programmable Output Slew Rate Control}
— Flexible Pin Placement
S _{— Optimized Global Routing Pool Provides Global}
L _{Interconnectivity}
p _{• ispDesignEXPERT™ – LOGIC COMPILER AND COM-}
is ^{PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL}
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
E _{— Tightly Integrated with Leading CAE Vendor Tools}
— Productivity Enhancing Timing Analyzer, Explore
S _{Tools, Timing Simulator and ispANALYZER™}
U^{— PC and UNIX Platforms}
Description
The ispLSI 2128V is a High Density Programmable Logic
Device available in 128 and 64 I/O-pin versions. The
device contains 128 Registers, eight Dedicated Input
pins, three Dedicated Clock Input pins, two dedicated
Global OE input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 2128V features in-
system programmability through the Boundary Scan
Test Access Port (TAP). The ispLSI 2128V offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2128V device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
September 2000
2128v_14
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