ISPLSI1016 Datasheet, PDF (6/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1016
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST ⁵
COND.
#²
DESCRIPTION¹
-80
-60
UNITS
MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT bypass, ORP bypass
– 15 – 20 ns
tpd2
A 2 Data Propagation Delay, Worst Case Path
– 20 – 25 ns
fmax (Int.)
A 3 Clock Frequency with Internal Feedback³
80 – 60 – MHz
fmax (Ext.)
W ^{fmax (Tog.)}
E ^tsu1
L _tco1
N _{IA th1}
R ^tsu2
R _tco2
O T _th2
F _{S tr1}
A ^{U trw1}
E ^{D ten}
tdis
16 ^{IN twh}
0 ^{S twl}
1 ^& N ^tsu5
I L ^th5
–
4
Clock
Frequency
with
External
Feedback_(tsu2
1
+
) _tco1
– 5 Clock Frequency, Max Toggle⁴
– 6 GLB Reg. Setup Time before Clock, 4PT bypass
A 7 GLB Reg. Clock to Output Delay, ORP bypass
– 8 GLB Reg. Hold Time after Clock, 4 PT bypass
– 9 GLB Reg. Setup Time before Clock
– 10 GLB Reg. Clock to Output Delay
– 11 GLB Reg. Hold Time after Clock
A 12 Ext. Reset Pin to Output Delay
– 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
C 15 Input to Output Disable
– 16 Ext. Sync. Clock Pulse Duration, High
– 17 Ext. Sync. Clock Pulse Duration, Low
– 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y2)
– 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y2)
50 – 38 – MHz
100 – 83 – MHz
7 – 9 – ns
– 10 – 13 ns
0 – 0 – ns
10 – 13 – ns
– 12 – 16 ns
0 – 0 – ns
– 17 – 22.5 ns
10 – 13 – ns
– 18 – 24 ns
– 18 – 24 ns
5 – 6 – ns
5 – 6 – ns
2 – 2.5 – ns
6.5 – 8.5 – ns
LS ^{IA IG 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.}
S _{2. Refer to Timing Model in this data sheet for further details.}
p ^{C 3. Standard 16-Bit loadable counter using GRP feedback.}
E _{4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.}
USCEOisMMER ^{D 5. Reference Switching Test Conditions Section.}
Table 2-0030-16/80,60C
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