ISPLSI1016 Datasheet, PDF (1/16 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

ispLSI^® 1016
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
W _{— Security Cell Prevents Unauthorized Copying}
E _{L • HIGH PERFORMANCE E2CMOS® TECHNOLOGY}
N ^{— fmax = 110 MHz Maximum Operating Frequency}
IA ^{— fmax = 60 MHz for Industrial and Military/883 Devices}
— tpd = 10 ns Propagation Delay
R _{R — TTL Compatible Inputs and Outputs}
— Electrically Erasable and Reprogrammable
O T _{— Non-Volatile E2CMOS Technology}
F _S — 100% Tested
• IN-SYSTEM PROGRAMMABLE
A ^U _{— In-System Programmable™ (ISP™) 5-Volt Only}
E ^{D — Increased Manufacturing Yields, Reduced Time-to-}
Market, and Improved Product Quality
16 ^{IN — Reprogram Soldered Devices for Faster Debugging}
• COMBINES EASE OF USE AND THE FAST SYSTEM
0 ^{S SPEED OF PLDs WITH THE DENSITY AND FLEX-}
& _{IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS}
1 N _{— Complete Programmable Device Can Combine Glue}
I L _{Logic and Structured Designs}
LS ^{IA IG — Three Dedicated Clock Input Pins}
— Synchronous and Asynchronous Clocks
S _{— Flexible Pin Placement}
p ^{C — Optimized Global Routing Pool Provides Global}
E _{Interconnectivity}
is ^{R D} • ispDesignEXPERT™ – LOGIC COMPILER AND COM-
E PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
E _{M — Superior Quality of Results}
S _{— Tightly Integrated with Leading CAE Vendor Tools}
U ^{M — Productivity Enhancing Timing Analyzer, Explore}
Tools, Timing Simulator and ispANALYZER™
CO ^{— PC and UNIX Platforms}
A0
B7
A1
DQ
B6
A2
DQ
B5
Logic
A3
Array D Q ^GLB
B4
A4
B3
DQ
A5
B2
A6
B1
A7 ^{Global Routing Pool (GRP)} B0
CLK
Description
The ispLSI 1016 is a High-Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1016 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1016 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. B7 (see figure 1). There are a total of 16 GLBs in the
ispLSI 1016 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
August 2000
1016_09
1