1032 Datasheet, PDF (6/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1032/883
Internal Timing Parameters¹
PARAMETER #² DESCRIPTION
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
20 I/O Register Bypass
21 I/O Latch Delay
22 I/O Register Setup Time before Clock
23 I/O Register Hold Time after Clock
24 I/O Register Clock to Out Delay
25 I/O Register Reset to Out Delay
26 Dedicated Input Delay
GRP
tgrp1
tgrp4
tgrp8
tgrp12
tgrp16
tgrp32
27 GRP Delay, 1 GLB Load
28 GRP Delay, 4 GLB Loads
29 GRP Delay, 8 GLB Loads
30 GRP Delay, 12 GLB Loads
31 GRP Delay, 16 GLB Loads
32 GRP Delay, 32 GLB Loads
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
tptre
tptoe
tptck
33 4 Product Term Bypass Path Delay
34 1 Product Term/XOR Path Delay
35 20 Product Term/XOR Path Delay
36 XOR Adjacent Path Delay³
37 GLB Register Bypass Delay
38 GLB Register Setup Time before Clock
39 GLB Register Hold Time after Clock
40 GLB Register Clock to Output Delay
41 GLB Register Reset to Output Delay
42 GLB Product Term Reset to Register Delay
43 GLB Product Term Output Enable to I/O Cell Delay
44 GLB Product Term Clock Delay
ORP
torp
45 ORP Delay
torpbp
46 ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.
-60
UNITS
MIN. MAX.
– 2.7 ns
– 4.0 ns
7.3 – ns
1.3 – ns
– 4.0 ns
– 3.3 ns
– 5.3 ns
– 2.0 ns
– 2.7 ns
– 4.0 ns
– 5.0 ns
– 6.0 ns
– 10.6 ns
– 8.6 ns
– 9.3 ns
– 10.6 ns
– 12.7 ns
– 1.3 ns
1.3 – ns
6.0 – ns
– 2.7 ns
– 3.3 ns
– 13.3 ns
– 12.0 ns
4.6 9.9 ns
– 3.3 ns
– 0.7 ns
6