1032 Datasheet, PDF (1/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

ispLSI^® 1032/883
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E²CMOS^® TECHNOLOGY
— fmax = 60 MHz Maximum Operating Frequency
— tpd = 20 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E²CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0
C7
A1
DQ
C6
A2
DQ
C5
Logic
A3
Array D Q ^GLB
C4
A4
C3
DQ
A5
C2
A6
C1
A7 ^{Global Routing Pool (GRP)} C0
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
Description
The ispLSI 1032/883 is a High-Density Programmable
Logic Device processed in full compliance to MIL-STD-
883. This military grade device contains 192 Registers,
64 Universal I/O pins, eight Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1032/883
features 5-Volt in-system programming and in-system
diagnostic capabilities. It is the first device which offers
non-volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 1032/883 device is
the Generic Logic Block (GLB). The GLBs are labeled A0,
A1 .. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032/883 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
September 2000
1032MIL_01
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