ORT8850 Datasheet, PDF (59/105 Pages) Agere Systems – Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

Lattice Semiconductor
ORCA ORT8850 Data Sheet
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
30009
Bit Type
Name
Reset
Value
(0x)
Description
TOH serial port
0 = AB TOH is output on AA
[0] R/W output MUX select 1 1 = AA TOH is output on AA
for AA/AB
TOH serial port
0 = AD TOH is output on AC
[1] R/W output MUX select 1 1 = AC TOH is output on AC
AC/AD
DOUT parallel port
0 = AB data is output on AA
[2] R/W output MUX select 1 1 = AA data is output on AA
for AA/AB
DOUT parallel port
0 = AD data is output on AC
[3] R/W output MUX select 1 1 = AC data is output on AC
for AC/AD
TOH serial port
0 = BB TOH is output on BA
[4] R/W output MUX select 1 1 = BA TOH is output on BA
for BA/BB
3000A
3000B
[5]
[6]
[7]
[0:4]
[5-7]
[0:4]
[5-7]
TOH serial port
R/W output MUX select
for BC/BD
0 = BD TOH is output on BC
1 1 = BC TOH is output on BC
DOUT parallel port
0 = BB data is output on BA
R/W output MUX select 1 1 = BA data is output on BA
for BA/BB
DOUT parallel port
0 = BD data is output on BC
R/W output MUX select 1 1 = BC data is output on BC
BC/BD
FIFO aligner
threshold value
(min)
R/W
Minimum threshold value for the per channel receive direction
alignment FIFOs. If and when the minimum threshold value is
violated by a particular channel, then the “FIFO aligner thresh-
40
decimal
2
old error” alarm bit will be generated for that channel and if
enabled, latched as a “FIFO aligner threshold error flag” in the
respective channel alarm register.
The allowable range for minimum threshold values is 1 to 23.
Note that the minimum FIFO aligner threshold value applies to
all eight channels.
MSB bit is 4.
- Not Used
N/A
FIFO aligner
- threshold value
(max)
A8 The allowable range for maximum threshold values is 0 to 22.
decimal MSB bit is 4
15
- Not Used
N/A
59