ORT8850 Datasheet, PDF (53/105 Pages) Agere Systems – Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

Lattice Semiconductor
ORCA ORT8850 Data Sheet
Figure 29 shows the timing for sending data from the FPGA logic to the Core. In the input case, the constraints on
the data are specified in terms of setup and hold times on the data at the interface relative to the clock at the inter-
face. For correct operation these constraints must be met. In the case shown, launch and capture occur on the
same (rising) clock edge. Data is captured before the next data is launched, so there will be no hold margin prob-
lem. Launched data also has nearly a full clock period to become stable at the capture latch, so setup margin
should not be a problem.
Figure 29. Full Cycle, Align and Bypass Mode Input Configuration and Timing (-1 Speed Grade)
a.) Configuration
FPGA
Logic
Q
FPGA_CLK
+
Note: xx = [AA, AB, ..., BD]
DINxx[7:0]
Δt
Δt
D
+
Embedded
Core
RETIME_CLK
2.4 n^. s
3.0 ns
Primary Clock
FPGA_SYSCLK
1.4 ns
a.) Timing (ns)
0.0
4.7
FPGA_SYSCLK
- 1.7
FPGA_CLK
3.0
7.7
Launch
9.4
14.1
12.4
17.1
Hold
1.0
5.7
RETIME_CLK
setup time - 1.3
hold time = 2.3
Requirements on
DINxx[7:0]
Data Valid
10.4
15.1
Capture
53