ORLI10G Datasheet, PDF (48/80 Pages) Agere Systems – Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

Lattice Semiconductor
ORCA ORLI10G Data Sheet
Figure 33 shows the Receive (Embedded Line Interface to FPGA) timing for 2.5G mode where PLL_RX2 is
bypassed via the PLL_BYPASS external FPSC pin. The 0.9 ns minimum propagation delay and 2.7 ns maximum
propagation delay shown are approximate values for the embedded line interface in this scenario. In the waveform
shown, data will be time shifted at the FPGA capture register due to FPGA data path delay. Consult the ispLEVER
software, via the static timing analysis tool TRACE, for the exact timing values. The FPGA data path delay needs to
increase together with clock skew to avoid hold issues. The FPGA design should be checked for hold violations
with TRACE.
Figure 33. Receive Timing for 2.5G Mode with PLL Bypassed (-1 Speed Grade)
RX_CLK_IN[0]
(644 MHz)
D
FPGA Clock
Long Skew
3.5ns
RX_DAT_IN
Q
RX_CLK8_IN_MUX1
Clock
Divider
Secondary
Clock
FPGA Clock
Short Skew
D
0.5ns
Q
RX_CLK_IN_BUF
1.4ns
FPGA
Embedded Line Interface Core
RX_CLK_IN_BUF
(Reference Clock)
0.0ns
3.1ns
6.2ns
9.3ns
12.4ns
RX_CLK8_IN_MUX1
1.4ns
4.5ns
Launch
7.6ns
10.7ns
13.8ns
FPGA Clock
Short Skew
0.5ns
Hold
3.6ns
6.7ns
9.8ns
Capture
12.9ns
Data
0.9 ns Tpd_min
2.7 ns Tpd_max
FPGA Clock Long Skew
Potential hold violation.
4.0ns
Hold
7.1ns
10.2ns
13.3ns
Capture
48