ORLI10G Datasheet, PDF (1/80 Pages) Agere Systems – Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

ORCA^® ORLI10G
Quad 2.5Gbps, 10Gbps
Quad 3.125Gbps, 12.5Gbps Line Interface FPSC
January 2005
Data Sheet
Introduction
The Lattice ORCA Series 4-based ORLI10G FPSC combines a high-speed line interface with a flexible FPGA logic
core. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORLI10G consists
of an OIF standard compliant (OIF-SFI4-01.0) SFI-4.1 or IEEE^® 802.3ae compliant XSBI, 10 Gbits/s or 12.5 Gbits/s
transmit and 10 Gbits/s or 12.5 Gbits/s receive line interface.
Both transmit and receive interfaces consist of 16-bit LVDS data at up to 850 Mbits/s, integrated transmit and
receive programmable PLLs for data rate conversions between the line-side and system-side data rates, and a pro-
grammable logic interface at the system end for use with SONET/SDH, Ethernet, or OTN/digital wrapper with
strong FEC system device data standards. In addition to the embedded functionality, the device includes over 400k
of usable FPGA gates. The line interface includes logic to divide the data rate down to 212 MHz or less (1/4 line
rate) or 106 MHz or less (1/8 line rate) for transfer to the FPGA logic. The ORLI10G is designed to connect to a
plethora of industry standard devices on the line side. The programmable logic interface on the system side allows
direct connection to a 10 Gbits/s Ethernet MAC, a 10 Gbits/s SONET/SDH framer/data engine, or a 10 Gbits/s/12.5
Gbits/s digital wrapper/FEC framer/data engine.
For 10 Gbits/s Ethernet, the ORLI10G supports the Physical Coding Sublayer (PCS), interfaces to the Physical
Media Attachment (PMA), and connects to the system interface (host or switch) for the proposed IEEE 802.3ae 10
Gbits/s serial LAN PHY.
The ORLI10G FPSC is a high-speed programmable device for 10 Gbits/s data solutions. It can be used as the
interface between the line interface and the system interface in a variety of emerging networks, including 10 Gbits/s
SONET/SDH (OC-192/STM-48), 10 Gbits/s Optical Transport Networks (OTN) using digital wrapper and strong
FEC, or 10 Gbits/s Ethernet. Other functions include use in quad OC-48/ STM-16 SONET/SDH systems, interfaces
between quad OC-48/STM-16 and OC-192/STM-64 components, and use as a generic data transfer mechanism
between two devices at 10 Gbits/s rates. Data is received at the line interface and then sent to either a 4-bit or 8-bit
serial-to-parallel converter. On the transmit interface, either a 4-bit or 8-bit parallel-to-serial converter is used. Thus,
the data rate at the internal FPGA interface is either 1/4 or 1/8 the line rate.
The programmable PLLs on the ORLI10G provide for great flexibility in handling clock rate conversion due to differ-
ing amounts of overhead bits in various system data standards. For example, the ORLI10G can divide down the
STS-192/STM-64 SONET/SDH data line rate of 622 MHz by 4 to synchronize with a 155 MHz system clock, or the
12.5 Gbits/s Super-FEC data line rate of 781 MHz can be divided by 8 MHz to 98 MHz system clock or by 8 x 4/5 to
provide a 78 MHz system data rate.
Table 1. ORCA ORLI10G–Available FPGA Logic (equivalent to ORCA OR4E04)
Device
ORLI10G
PFU Rows
36
PFU Col-
umns
36
FPGA Max.
Total PFUs User I/Os*
1,296
316
LUTs
10,368
EBR
Blocks
12
EBR Bits
(k)
111
FPGA Sys-
tem Gates
(k)
333—643
* 316 are available in the 680 PBGAM package.
Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate
ranges are derived from the following: minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with
40% EBR usage and 2 PLLs. Maximum system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80%
EBR usage and 6 PLLs.
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brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
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