OR4 Datasheet, PDF (46/152 Pages) Lattice Semiconductor – ORCASeries 4 FPGAs

ORCA Series 4 FPGAs
Data Sheet
May, 2006
Special Function Blocks (continued)
The MODE signal is generated from the decode of the instruction register. When the MODE signal is high
(EXTEST), the scan data is propagated to the output buffer. When the MODE signal is low (BYPASS or SAMPLE),
functional data from the FPGA’s internal logic is propagated to the output buffer.
The boundary-scan description language (BSDL) is provided for each device in the ORCA Series of FPGAs on the
ispLEVER CD. The BSDL is generated from a device profile, pinout, and other boundary-scan information.
P_IN
SCAN IN
0
1
P_OUT
0
0
1
1
HOLI
CAPTURE CELL
DQ
DQ
DQ
INBS (TO FPGA ARRAY)
I/O BUFFER
PAD_IN
BIDIRECTIONAL DATA CELL
PAD_OUT
0
DQ
1
PAD_TS
P_TS
0
DQ
1
0
DQ
1
DIRECTION CONTROL CELL
SHIFTN/CAPTURE TCK
SCAN OUT UPDATE/TCK
Figure 29. Boundary-Scan Cell
MODE
5-2844(F).a
Boundary-Scan Timing
To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on the
rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST
instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum fre-
quency allowed for TCK is 20 MHz.
Figure 30 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to
sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is
clocked into the DUT on the rising edge.
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