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ISPCLOCK5300S Datasheet, PDF (4/56 Pages) Lattice Semiconductor – In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 4. ispClock5316S Functional Block Diagram
LOCK
RESET
PLL_ BYPASS OEX OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
0
1
REFSEL
FBK
VTT_FBK
LOCK
DETECT
PHASE
DETECT
LOOP
FILTER
VCO
JTAG INTERFACE
TDI TMS TCK TDO
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
SKEW
OUTPUT
MATRIX
CONTROL DRIVERS
OUTPUT
DIVIDERS
BANK _0 A
1
V0
BANK _0 B
0
5-bit
BANK _1 A
BANK _1 B
V1
5-bit
BANK _2 A
BANK _2 B
V2
5-bit
BANK _3 A
SKEW
CONTROL
OUTPUT
DRIVERS
BANK _3 B
BANK _4 A
BANK _4 B
BANK _5 A
BANK _5 B
BANK _6 A
BANK _6 B
BANK _7 A
BANK _7 B
Figure 5. ispClock5320S Functional Block Diagram
LOCK
RESET
PLL_ BYPASS OEX OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
0
1
REFSEL
FBK
VTT_FBK
LOCK
DETECT
PHASE
DETECT
LOOP
FILTER
VCO
JTAG INTERFACE
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
SKEW
OUTPUT
MATRIX
CONTROL DRIVERS
OUTPUT
DIVIDERS
BANK_0A
1
V0
BANK_0B
0
5-bit
BANK_1A
BANK_1B
V1
5-bit
BANK_2A
BANK_2B
V2
5-bit
BANK_3A
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
BANK_6A
BANK_6B
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
BANK_9B
TDI TMS TCK TDO
4