ISPCLOCK5300S Datasheet, PDF (22/56 Pages) Lattice Semiconductor – In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended

Lattice Semiconductor
ispClock5300S Family Data Sheet
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal can be connected to either the REFA
or REFB pins. CMOS transmission lines are generally source terminated, so all termination resistors should be set
to the OPEN state. Figure 15 shows the proper configuration. Please note that because switching thresholds are
different for LVCMOS running at 1.8V, there is a separate configuration setting for this particular standard. Unused
reference inputs and VTT pins should be grounded.
Figure 15. LVCMOS/LVTTL Input Receiver Configuration
REFA_REFP /
REFB_REFN _RT
VTT_REFA /
VTT_REFB _GND
Single-ended
Receiver
Open
HSTL, eHSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal can be connected to the REFA or REFB ter-
minal of the input pair and the associated VTT_REFA or VTT_REFB terminal should be tied to a VTT termination
supply. The terminating resistor should be set to 50Ω and the engaging switch should be closed. Figure 16 shows
an appropriate configuration. Refer to the “Recommended Operating Conditions - Supported Logic Standards”
table in this data sheet for suitable values of V_REF and V_TT.
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator specifically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 16. SSTL2, SSTL3, eHSTL, HSTL Receiver Configuration
REFA_REFP /
REFB_REFN
50
VTT_REFA /
VTT_REFB
Single-ended
Receiver
Closed
Differential LVPECL/LVDS
The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be
engaged and set to 50Ω. The VTT_REFA and VTT_REFB pins, however, should be connected. This creates a float-
ing 100Ω differential termination resistance across the input terminals. The LVDS termination configuration is
shown in Figure 17.
Note: the REFSEL pin should be grounded when the input receiver is configured as differential.
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