2096E Datasheet, PDF (4/11 Pages) Lattice Semiconductor – In-System Programmable SuperFAST™ High Density PLD

Specifications ispLSI 2096E
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
1.5 ns
1.5V
1.5V
See Figure 2
Table 2-0003/2128E
Output Load Conditions (see Figure 2)
TEST CONDITION
A
Active High
B
Active Low
Active High to Z
C
at V_OH -0.5V
Active Low to Z
at V_OL +0.5V
R1
470Ω
∞
470Ω
∞
R2
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
470Ω
390Ω 5pF
Table 2 - 0004A/2000
Figure 2. Test Load
Device
Output
+ 5V
R1
R2
Test
Point
CL*
*CL includes Test Fixture and Probe Capacitance.
0213A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN. TYP.³ MAX. UNITS
VOL ^{Output Low Voltage}
I_OL = 8 mA
–
–
0.4
V
VOH ^{Output High Voltage}
I_OH = -4 mA
2.4
–
–
V
IIL
Input or I/O Low Leakage Current
0V ≤ V_IN ≤ V_IL (Max.)
–
–
-10 µA
IIH
Input or I/O High Leakage Current
(V_CCIO - 0.2)V ≤ V_IN ≤ V_CCIO
V_CCIO ≤ V_IN ≤ 5.25V
–
–
10 µA
–
–
10 µA
IIL-PU I/O Active Pull-Up Current
0V ≤ V_IN ≤ 2.0V
-10
– ^-250 µA
IOS¹ Output Short Circuit Current
V_CCIO = 5.0V or 3.3V, V_OUT = 0.5V
–
– -240 mA
ICC^3,4 Operating Power Supply Current
V_IL = 0.0V, V_IH = 3.0V
f_TOGGLE = 1 MHz
–
130
–
mA
1. One output at a time for a maximum duration of one second. V_OUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
Table 2-0007/2096E
2. Meaured using six 16-bit counters.
3. Typical values are at V_CC = 5V and T_A = 25°C.
4. Unused inputs held at 0.0V.
5. Maximum I_CC varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum I_CC.
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