ISPMACH4ACPLDFAMILY Datasheet, PDF (38/62 Pages) Lattice Semiconductor – High Performance E 2 CMOS In-System Programmable Logic

ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES¹
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Combinatorial Delay:
t_PDi
Internal combinatorial propagation
delay
3.5
4.0
4.3
4.5
5.0
7.0
9.0
11.0 ns
t_PD Combinatorial propagation delay
Registered Delays:
5.0
5.5
6.0
6.5
7.5
10.0
12.0
14.0 ns
t_SS
Synchronous clock setup time, D-type
register
3.0
3.5
3.5
3.5
5.0
5.5
7.0
10.0
ns
t_SST
Synchronous clock setup time, T-type
register
4.0
4.0
4.0
4.0
6.0
6.5
8.0
11.0
ns
Asynchronous clock setup time, D-type
t_{SA register}
2.5
2.5
2.5
3.0
3.5
4.0
5.0
8.0
ns
t_SAT
Asynchronous clock setup time, T-type
register
3.0
3.0
3.0
3.5
4.5
5.0
6.0
9.0
ns
t_HS Synchronous clock hold time
t_HA Asynchronous clock hold time
t_COSi Synchronous clock to internal output
t_COS Synchronous clock to output
t_COAi Asynchronous clock to internal output
t_COA Asynchronous clock to output
Latched Delays:
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
2.5
2.5
2.5
3.0
3.5
4.0
5.0
8.0
ns
2.5
2.5
2.8
3.0
3.0
3.0
3.5
3.5 ns
4.0
4.0
4.5
5.0
5.5
6.0
6.5
6.5 ns
5.0
5.0
5.0
5.0
6.0
8.0
10.0
12.0 ns
6.5
6.5
6.8
7.0
8.5
11.0
13.0
15.0 ns
t_SSL Synchronous latch setup time
t_SAL Asynchronous latch setup time
t_HSL Synchronous latch hold time
t_HAL Asynchronous latch hold time
t_PDLi Transparent latch to internal output
t_PDL
Propagation delay through transparent
latch to output
4.0
4.0
4.0
4.5
6.0
7.0
8.0
10.0
ns
3.0
3.0
3.5
3.5
4.0
4.0
5.0
8.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
3.0
3.0
3.5
3.5
4.0
4.0
5.0
8.0
ns
5.5
5.5
5.8
6.0
7.5
9.0
11.0
12.0 ns
7.0
7.0
7.5
8.0
10.0
12.0
14.0
15.0 ns
t_GOSi Synchronous gate to internal output
t_GOS Synchronous gate to output
t_GOAi Asynchronous gate to internal output
t_GOA Asynchronous gate to output
Input Register Delays:
3.0
3.0
3.0
3.0
3.5
4.5
7.0
8.0 ns
4.5
4.5
4.8
5.0
6.0
7.5
10.0
11.0 ns
6.0
6.0
6.0
6.0
8.5
10.0
13.0
15.0 ns
7.5
7.5
7.8
8.0
11.0
13.0
16.0
18.0 ns
t_SIRS Input register setup time
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
ns
t_HIRS Input register hold time
2.5
2.5
3.0
3.0
3.0
3.0
3.0
4.0
ns
t_ICOSi Input register clock to internal feedback
3.0
3.0
3.0
3.0
3.5
4.5
6.0
6.0 ns
Input Latch Delays:
t_SIL Input latch setup time
t_HIL Input latch hold time
t_IGOSi Input latch gate to internal feedback
t_PDILi
Transparent input latch to internal
feedback
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
ns
2.5
2.5
2.5
3.0
3.0
3.0
3.0
4.0
ns
3.5
3.5
3.8
4.0
4.0
4.0
4.0
5.0 ns
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0 ns
38
ispMACH 4A Family