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ISPMACH4ACPLDFAMILY Datasheet, PDF (1/62 Pages) Lattice Semiconductor – High Performance E 2 CMOS In-System Programmable Logic | |||
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ispMACH⢠4A CPLD Family
High Performance E2CMOS®
In-System Programmable Logic
FEATURES
x High-performance, E2CMOS 3.3-V & 5-V CPLD families
x Flexible architecture for rapid logic designs
â Excellent First-Time-FitTM and reï¬t feature
â SpeedLockingTM performance for guaranteed ï¬xed timing
â Central, input and output switch matrices for 100% routability and 100% pin-out retention
x High speed
â 5.0ns tPD Commercial and 7.5ns tPD Industrial
â 182MHz fCNT
x 32 to 512 macrocells; 32 to 768 registers
x 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
x Flexible architecture for a wide range of design styles
â D/T registers and latches
â Synchronous or asynchronous mode
â Dedicated input registers
â Programmable polarity
â Reset/ preset swapping
x Advanced capabilities for easy system integration
â 3.3-V & 5-V JEDEC-compliant operations
â JTAG (IEEE 1149.1) compliant for boundary scan testing
â 3.3-V & 5-V JTAG in-system programming
â PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
â Safe for mixed supply voltage system designs
â Programmable pull-up or Bus-FriendlyTM inputs and I/Os
â Hot-socketing
â Programmable security bit
â Individual output slew rate control
x Advanced E2CMOS process provides high-performance, cost-effective solutions
x Supported by ispDesignEXPERTTM software for rapid logic development
â Supports HDL design methodologies with results optimized for ispMACH 4A
â Flexibility to adapt to user requirements
â Software partnerships that ensure customer success
x Lattice and third-party hardware programming support
â LatticePROTM software for in-system programmability support on PCs and automated test
equipment
â Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication# ISPM4A Rev: D
Amendment/0
Issue Date: August 2000
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