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TN1112 Datasheet, PDF (3/6 Pages) Lattice Semiconductor – Input Hysteresis in Lattice CPLD and FPGA Devices | |||
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Lattice Semiconductor
Figure 5. Input Measured at Point A
Input Hysteresis in
Lattice CPLD and FPGA Devices
Figure 6. Zoomed View of Rising Edge of Figure 5
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