TN1112 Datasheet, PDF (1/6 Pages) Lattice Semiconductor – Input Hysteresis in Lattice CPLD and FPGA Devices

Input Hysteresis in Lattice CPLD and
FPGA Devices
September 2006
Technical Note TN1112
Introduction
In order to optimize speed in Lattice devices such as the ispMACH™ 4000 and MachXO™, device inputs are con-
figurable with internal pull-up, pull-down, bus-hold latch or no bus maintenance. Typically, inputs can tolerate rise
and fall times in the 50ns to 100ns range. When interfacing to slow input signals with input rise and fall time in hun-
dreds of nanoseconds, external board design techniques are necessary to make the slow input signals immune to
input noise that may be injected. This technical note suggests a few such techniques.
Input Circuit Techniques
Simple external circuitry along with the internal bus maintenance circuit can significantly improve slow rising and
falling input noise immunity. Three common methods are described below.
Figure 1. Method 1: Input Series Resistor
Cin
20
59
Cout
Figure 2. Method 2: Input and Feedback Resistor
HCout
21
Cin
20
Figure 3. Method 3: Input Resistor and Feedback Capacitor
HCout
21
59
Cout
Cin
20
59
Cout
The following experimental data was collected to demonstrate the improvement that can be achieved with the dif-
ferent methods as compared to inputs without any external circuitry. The tables below highlight the maximum input
rise (t_RISE) and fall (t_FALL) time of the results.
Test Device: MachXO
I/O Standard: LVCMOS 3.3V with input bus-hold latch turned on
Temperature: Room temperature
External Input Circuit
None
Method 1
Input Series Resistor
—
100Ω
470Ω
680Ω
t_RISE
<54ns
65ns
500ns
>15ms
t_FALL
<56ns
63ns
470ns
>15ms
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