5962-8983902RA Datasheet, PDF (3/8 Pages) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic™

Specifications GAL16V8D-7/10/883
AC Switching Characteristics
Over Recommended Operating Conditions
TEST
PARAMETER _COND1.
DESCRIPTION
tpd
A
Input or I/O to Combinational Output
tco
A
Clock to Output Delay
tcf²
— Clock to Feedback Delay
tsu
— Setup Time, Input or Feedback before Clock↑
th
— Hold Time, Input or Feedback after Clock↑
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
fmax³
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
No Feedback
twh
— Clock Pulse Duration, High
twl
— Clock Pulse Duration, Low
ten
B
Input or I/O to Output Enabled
B
OE to Output Enabled
tdis
C
Input or I/O to Output Disabled
C
OE to Output Disabled
-7
MIN. MAX.
1 7.5
-10
MIN. MAX.
2 10
UNITS
ns
1
6
1
7
ns
—6—7
ns
7
— 10 —
ns
0
—
0
—
76.9 — 58.8 —
ns
MHz
76.9 — 58.8 — MHz
100 — 62.5 — MHz
5
—
8
—
ns
5
—
8
—
ns
1
9
— 10
ns
1
7
— 10
ns
1
9
— 10
ns
1
7
— 10
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.
Capacitance (T_A = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
C_I
Input Capacitance
C_I/O
I/O Capacitance
*Characterized but not 100% tested.
MAXIMUM*
10
10
UNITS
pF
pF
TEST CONDITIONS
V_CC = 5.0V, V_I = 2.0V
V_CC = 5.0V, V_I/O = 2.0V
3