ISPCLOCK5600 Datasheet, PDF (20/47 Pages) Lattice Semiconductor – In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer

Lattice Semiconductor
Figure 14. LVCMOS/LVTTL Input Receiver Configuration
ispClock5600
Signal In
REFA+
ispClock5600 Family Data Sheet
Single-ended
Receiver
No Connect
REFA-
R
T
No Connect
REFVTT
OPEN
HSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input
pair. The ‘-’ input terminal should be tied to the appropriate V_REF value, and the associated REFVTT or FBKVTT
terminal should be tied to a V_TT termination supply. The positive input’s terminating resistor should be engaged and
set to 50Ω. Figure 15 shows an appropriate configuration. Refer to the “Recommended Operating Conditions -
Supported Logic Standards” table in this data sheet for suitable values of V_REF and V_TT.
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator specifically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 15. SSTL2, SSTL3, HSTL Receiver Configuration
ispClock5600
Signal In
REFA+
Differential
Receiver
VREF IN
REFA-
50
VTT
REFVTT
CLOSED OPEN
20