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ISPCLOCK5600 Datasheet, PDF (1/47 Pages) Lattice Semiconductor – In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer | |||
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ispClockâ¢5600 Family
In-System Programmable, Zero-Delay Clock Generator
with Universal Fan-Out Buffer
November 2004
Preliminary Data Sheet
Features
â 10MHz to 320MHz Input/Output Operation
â Low Output to Output Skew (<50ps)
â Low Jitter Peak-to-Peak (<60ps)
â Up to 20 Programmable Fan-out Buffers
⢠Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS,
LVPECL
⢠Programmable output impedance
- 40 to 70⦠in 5⦠increments
⢠Programmable slew rate
⢠Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
â Fully Integrated High-Performance PLL
⢠Programmable lock detect
⢠Multiply and divide ratio controlled by
- Input divider (5 bits)
- Feedback divider (5 bits)
- Five output dividers (5 bits)
⢠Programmable On-chip Loop Filter
â Precision Programmable Phase Adjustment
(Skew) Per Output
⢠16 settings; minimum step size 195ps
- Locked to VCO frequency
Product Family Block Diagram
⢠Up to +/- 12ns skew range
⢠Coarse and ï¬ne adjustment modes
â Up to Five Clock Frequency Domains
â Flexible Clock Reference and External
Feedback Inputs
⢠Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL
⢠Clock A/B selection multiplexer
⢠Feedback A/B selection multiplexer
⢠Programmable termination
â Four User-programmable Proï¬les Stored in
E2CMOS® Memory
⢠Supports both test and multiple operating
conï¬gurations
â Full JTAG Boundary Scan Test In-System
Programming Support
â Exceptional Power Supply Noise Immunity
â Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
â 100-pin and 48-pin TQFP Packages
â Applications
⢠Circuit board common clock generation and
distribution
⢠PLL-based frequency generation
⢠High fan-out clock buffer
⢠Zero-delay clock buffer
LOCK DETECT
OUTPUT
BYPASS
DIVIDERS
V0
SKEW
OUTPUT
CONTROL DRIVERS
MUX
V1
M
*
PHASE/
V2
FREQUENCY
FILTER
VCO
DETECTOR
V3
N
PLL CORE
V4
OUTPUT
ROUTING
MATRIX
Internal/External
Feedback
Select
JTAG
INTERFACE
&
Multiple Profile
Management Logic
*
E2CMOS
MEMORY
0123
* Input Available only on ispClock5620
INTERNAL FEEDBACK PATH
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speciï¬cations and information herein are subject to change without notice.
www.latticesemi.com
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