ISPLSI5384VE-125LB272 Datasheet, PDF (18/22 Pages) Lattice Semiconductor – In-System Programmable 3.3V SuperWIDE™ High Density PLD

Specifications ispLSI 5384VE
Power Consumption
Power consumption in the ispLSI 5384VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of product terms
used. The product terms have a fuse-selectable speed/
power tradeoff setting. Each group of five product terms
has a single speed/power tradeoff control fuse that acts
on the complete group of five. The fast “high-speed”
setting operates product terms at their normal full power
consumption. For portions of the logic that can tolerate
longer propagation delays, selecting the slower “low-
power” setting will reduce the power dissipation for these
product terms. Figure 10 shows the relationship between
power and operating frequency.
Figure 10. Typical Device Power Consumption vs fmax
460
420
380
340
300
260
220
0
ispLSI 5384VE
High Speed Mode
ispLSI 5384VE
Low Power Mode
25 50 75 100 125 150 175 200
fmax (MHz)
Notes: Configuration of 24 16-bit Counters
Typical Current at 3.3V, 25° C
ICC can be estimated for the ispLSI 5384VE using the following equation:
High Speed Mode: ICC = 22 + (# of PTs * 0.314) + (# of nets * Fmax * 0.00317)
Low Power Mode: ICC = 22 + (# of PTs * 0.271) + (# of nets * Fmax * 0.00317)
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Fmax = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of one GLB load
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
0127/5384VE
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