ML7037-003 Datasheet, PDF (9/87 Pages) LAPIS Semiconductor Co., Ltd. – Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free

FEDL7037-003-03
ML7037-003
LINN, LGSX
These are the line analog input and level tuning pins. The LINN pin is connected to the inverting input of the
internal amp (AMP3) and the LGSX pin is connected to the output of the amp (AMP3). For level tuning, refer to
Figure 3 Analog Interface.
During power-down mode (PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’), the LGSX pin goes to a high
impedance state.
(Note) When the line side analog interface is not used, set the secondary function of the GPIB1 pin (LINEEN) to
logic ‘1’ or set the LINEEN-bit [CR0-B5] to ‘1’, and short the LINN pin and the LGSX pin.
AVFRO, LVFRO
These are analog output pins respectively for acoustic-side and line-side. The AVFRO is connected to the output of
the internal amp (AMP4), and the LVFRO is connected to the output of the internal amp (AMP5).
The output state of the AVFRO pin and the LVFRO pin can be selected between speech signal output and the
AVREF level output (1.4V approx.) by the VFROSEL pin or by the AVFROSEL-bit [CR16-B1] and the
LVFROSEL-bit [CR16-B0]. When the concerned pin or the concerned bit is logic ‘1’, the AVFRO and/or the
LVFRO pin outputs speech signals; when the concerned pin and the concerned bit is logic ‘0’, the AVFRO pin
and/or the LVFRO pin outputs the AVREF level (1.4V approx.).
During power-down mode (PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’), if the AVREFEN pin and the
AVREFEN-bit [CR16-B7] are logic ‘0’, the AVFRO pin and the LVFRO pin go to a high impedance state; and, if
the AVREFEN pin or the AVREFEN-bit [CR16-B7] are logic ‘1’, the pins output 1.4V approx..
(Note) If the AVREFEN pin and the AVREFEN-bit [CR16-B7] are logic ‘0’, pop noises may occur on release
and execution of power-down. If the AVREFEN pin and the AVREFEN-bit [CR16-B7] need to be logic
‘0’ and still the pop noises have to be eliminated, it has to be fixed outside of this LSI.
To avoid the pop noises, set the AVREFEN pin or the AVREFEN-bit [CR16-B7] to logic ‘1’ and let the
AVREF and the analog output amps alive. Furthermore, the power-down should be released and executed
having the output state of the AVFRO pin and the LVFRO pin the AVREF level.
In concrete, the power-down should be released while keeping the VFROSEL pin and by the
AVFROSEL-bit [CR16-B1] and the LVFROSEL-bit [CR16-B0] to logic ‘0’, and then change the
VFROSEL pin or the AVFROSEL-bit [CR16-B1] and the LVFROSEL-bit [CR16-B0] to logic ‘1’.
And, the VFROSEL pin and the AVFROSEL-bit [CR16-B1] and the LVFROSEL-bit [CR16-B0] should
be changed to logic ‘0’ before the power-down execution.
Please note that the power supply current during the power-down would be I_SS2 compliant (Please refer to
the specification under the DC Characteristics to come in a later section.) if the AVREFEN pin or the
AVREFEN-bit [CR16-B7] are logic ‘1’.
AVREF
This is the output pin for the analog signal ground level. The output voltage is approximately 1.4 V.
Insert a 10 µF bypass capacitor (a tantalum capacitor [recommendation] or an aluminum electrolytic capacitor) and
a 0.1 µF capacitor (laminating ceramic type) in parallel between this pin and the AGND0 pin.
During power-down mode (PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’) with the AVREFEN pin and the
AVREFEN-bit [CR16-B7] to be logic ‘0’, the AVREF pin outputs 0.0V.
During power-down mode (PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’) with the AVREFEN pin or the
AVREFEN-bit [CR16-B7] to be logic ‘1’, the AVREF pin outputs 1.4V approx..
(Note) If you make use of the AVREF pin output externally in your system, it must be via a buffer amp.
AVREFEN
This is to select disabling and enabling the AVREF output during power-down mode (PDN pin = logic ‘0’ or
SPDN-bit [CR0-B7] = ‘1’).
When this is logic ‘0’, the AVREF pin is disabled (power-down state).
When this is logic ‘1’, the AVREF pin is enabled, and the outputs of the AVREF, the AVFRO and the LVFRO
become 1.4V approx..
This pin control is valid only during power-down.
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