ML7037-003 Datasheet, PDF(36/87 Page) LAPIS Semiconductor Co., Ltd. – Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free

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ML7037-003 Datasheet, PDF (36/87 Pages) LAPIS Semiconductor Co., Ltd. – Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free

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FEDL7037-003-03

ML7037-003

(2) CR1

CR1

DMWR

When to alter

I/E

Initial value

B7 : Internal Data Memory Write Execution Register

0 : Write inhibited

1 : Write

A logic â1â in this register transfers the data specified by the CR8 (D15-D8) and the CR9 (D7-D0) into the internal

data memory address specified by the CR6 (D15-D8) and the CR7 (D7-D0). After the completion of the data

transfer, this register bit is automatically cleared to a logic â0â.

Confirm if this register bit turns to a logic â0â before another internal data memory write is made.

For more details, refer to descriptions under Internal Data Memory Access.

B6-B0 : Reserved bits â¦ Do not alter the initial values.

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