MK71251-01 Datasheet, PDF (4/29 Pages) LAPIS Semiconductor Co., Ltd. – Bluetooth Smart wireless module

FEDK71251-01
MK71251-01/MK71251-02
■ Pin definitions
I/O symbol IRF ： RF input and output
I
： Digital input
Is
： Digital input with shmit.
IAH ： Analog input support 3V
XSH ： X’tal pin for Low-Power Clock
O2 ： Digital output with 2mA load capability
B2 ： Digital inout with 2mA load capability
B2PD ： Digital inout with 2mA load capability and pull-down resistor
B2PU ： Digital inout with 2mA load capability and and pull-up resistor
No
Pin name
Status/Value I/O
Active
Function
at reset
Level
1 NC
---
---
---
NC pin
2 OUT_ANT
Output from Antenna
---
IRF
---
(to be connected to OUT_MOD by user's PCB)
3 OUT_MOD
Output from Module
---
IRF
---
(to be connected to OUT_ANT by user's PCB)
4 SWREG_FB
1.35V/3.0V
Input
---
---
Switching regulator pin.
Please use this pin open.
5 T1
6 T0
7 RESETB
Hi-Z
Hi-Z
Input
IAH
---
Test pin 0
IAH
---
Test pin 1
Is
Low Reset input (Low = Reset)
8 TMODE
Input
I
---
TEST MODE input (Fixed to Low)
9 TMON
10 SWD
Input
Input
XSH
---
Test monitor pin. Please use this pin open.
B2
---
SWD data inout
11 GND
---
---
---
GND
12 SWCK
Input
I
---
SWD clock input
13 PS_CONTROL/GPIO3 _{Output Low}
B2
---
PS_CONTROL output(MK71251-01)
GPIO3:GPIO inout3 (MK71251-02)
14 I2C_SDA
Input
B2PU
---
I2C_SDA monitor pin.
15 I2C_SCL
Input
B2PU
---
I2C_SCL monitor pin.
16 IRQ/GPIO2
Output High
B2
---
IRQ output(MK71251-01)
GPIO2:GPIO inout2 (MK71251-02)
17 VDDBAT
---
---
---
Power supply 2.0 to 3.6V
18 RF_ACTIVE/GPIO0
Output Low
B2
---
RF_ACTIVE output(MK71251-01)
GPIO0:GPIO inout0 (MK71251-02)
19 WAKEUP/GPIO1
Input
B2
WAKEUP input(MK71251-01)
---
GPIO1:GPIO inout1 (MK71251-02)
20 GND
---
---
---
GND
21 UART_TXD
22 UART_RXD
Output High
Input
O2
B2PD
---
UART TXD output
---
UART RXD input
23 SPIDIN/TM1
Input
SPIDIN:SPI Data input(MK71251-01)
I
---
TM1:Test mode input1(MK71251-02)
24 SPIDOUT/TM2
Input
B2PD
---
SPIDOUT:SPI Data output(MK71251-01)
TM2: Test mode input2 (MK71251-02)
25 SPIXCS/TM3
Input
I
Low
SPIXCS:SPI Chip Select(MK71251-01)
TM3: Test mode input3 (MK71251-02)
26 SPICLK/TM4
27 FETGATE
Input
Input
SPICLK:SPI Clock(MK71251-01)
I
---
TM4: Test mode input4 (MK71251-02)
I
---
FET Gate control pin.、
(To be connected to PS_SW by user's PCB.)
28 PS_SW
Output Low
O2
---
Status pin indicates deep sleep mode status.
29 NC
---
---
---
NC pin
30 GND
---
---
---
GND
31 GND
---
---
---
GND
32 GND
---
---
---
GND
33 GND
---
---
---
GND
4/29