ML7204-003 Datasheet, PDF (107/214 Pages) LAPIS Semiconductor Co., Ltd. – VoIP CODEC

FEDL7204-003-02
ML7204-003
Table 7 lists the transmit/receive buffer control registers.
Note that the register that is referenced or set on the MCU side varies depending on the operating mode
(1-channel operation/2-channel operation) of Speech CODEC.
Table 7 Transmit/Receive Buffer Control Registers
CR Bit
Register name (abbreviation)
Single-channel
operation
SC_EN=1,DC_EN=0
CR21 B0 CH1 transmit request notification register (FR0_CH1)

B1 CH2 transmit request notification register (FR0_CH2)

B2 CH1 transmit error status register (TXERR_CH1)

B3 CH2 transmit error status register (TXERR_CH2)

B4 Transmit frame start notification register (TXREQ_First)

B5 2-channel transmit request notification register

(TXREQ_DC)
B6 Transmit side buffering time operating mode notification

flag
(TX_BTFLAG)
B7 Transmit side Speech CODEC operating mode

notification flag
(TX_SCFLAG)
CR22 B0 Receive request notification register (FR1)

B1 Invalid receive data write error notification register

(RXBW_ERR)
B2 CH1 receive error status register (RXERR_CH1)

B3 CH2 receive error status register (RXERR_CH2)

B4 Receive frame start notification register (RXREQ_First)

B5 2-channel receive request notification register

(RXREQ_DC)
B6 Receive side buffering time operating mode notification

flag
(RX_BTFLAG)
B7 Receive side Speech CODEC operating mode

notification flag
(RX_SCFLAG)
CR5 B1- Receive data write channel notification register

B0 RXFLAG_[CH2:CH1]
(Remarks) : Used, : Unused
2-channel operation
SC_EN=1,DC_EN=1
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