ML7204-003 Datasheet, PDF (104/214 Pages) LAPIS Semiconductor Co., Ltd. – VoIP CODEC

FEDL7204-003-02
ML7204-003
B1: CH2 transmit request notification register
0: No CH2 transmit request generated
1: CH2 transmit request generated
When the transmit buffer storing the CH2 transmit data becomes full, this bit is set to “1” and the bit is set to “0”
at completion of reading of the data from the transmit buffer or the processing time exceeded the specified time.
B0: CH1 transmit request notification register
0: No CH1 transmit request generated
1: CH1 transmit request generated
When the transmit buffer storing CH1 transmit data becomes full, this bit is set to “1” and the bit is set to
“0” at completion of reading of the data from the transmit buffer or the processing time exceeded the
specified time.
In frame mode (FD_SEL = 0), the signal obtained by NORing bit B1 with bit B0 is output to the FR0B pin. (*)
(Note)*
In DMA mode (FD_SEL = 1), the bit B1, bit B0, and FR0B (DMARQ0B) pin statuses do not match.
When the setting of the bits B3-B2 (“0”  “1” or “1”  “0” ) or bits B1-B0 (“0”  “1”) changes, an INTB
interrupt occurs.
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