KK74ACT112 Datasheet, PDF (3/6 Pages) KODENSHI KOREA CORP. – Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

KK74ACT112
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
V_CC Guaranteed Limits
V 25 °C -40°C to Unit
85°C
V_IH Minimum High-
V_OUT=0.1 V or V_CC - 0.1 V 4.5
2.0
2.0
V
Level Input Voltage
5.5
2.0
2.0
V_IL Maximum Low -
V_OUT=0.1 V or V_CC - 0.1 V 4.5
0.8
0.8
V
Level Input Voltage
5.5
0.8
0.8
V_OH Minimum High-
I_OUT ≤ -50 µA
Level Output Voltage
*_{VIN= VIL or VIH}
I_OH=-24 mA
I_OH=-24 mA
V_OL Maximum Low-
I_OUT ≤ 50 µA
Level Output Voltage
*_{VIN= VIL or VIH}
I_OL=24 mA
I_OL=24 mA
I_IN
Maximum Input
Leakage Current
V_IN=V_CC or GND
4.5
4.4
4.4
V
5.5
5.4
5.4
4.5 3.86
3.76
5.5 4.86
4.76
4.5
0.1
0.1
V
5.5
0.1
0.1
4.5 0.36
0.44
5.5 0.36
0.44
5.5 ±0.1
±1.0
µA
∆I_CCT Additional Max
V_IN=V_CC - 2.1 V
5.5
I_CC/Input
I_OLD +Minimum Dynamic V_OLD=1.65 V Max
5.5
Output Current
1.5
mA
75
mA
I_OHD +Minimum Dynamic V_OHD=3.85 V Min
5.5
Output Current
-75
mA
I_CC
Maximum Quiescent V_IN=V_CC or GND
Supply Current
(per Package)
5.5
4.0
* _{All outputs loaded; thresholds on input associated with output under test.}
+Maximum test duration 2.0 ms, one output loaded at a time.
40
µA
3