KK74ACT112 Datasheet, PDF (1/6 Pages) KODENSHI KOREA CORP. – Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

TECHNICAL DATA
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
KK74ACT112
The KK74ACT112 is identical in pinout to the LS/ALS112,
HC/HCT112. The KK74ACT112 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74ACT112N Plastic
KK74ACT112D SOIC
T_A = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V_CC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K
Q
Q
L
H
X
XX H
L
H
L
L
L
X
XX L
H
X
XX
L^*
L^*
H
H
L L No Change
H
H
LH L
H
H
H
HL H
L
H
H
HH
Toggle
H
H
L
X X No Change
H
H
H
X X No Change
H
H
X X No Change
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
1