DDR4-FUNCTIONAL Datasheet, PDF (2/10 Pages) Keysight Technologies – DDR4 Functional/Protocol Debug and Analysis Reference Solution

02 | Keysight | DDR4 Functional/Protocol Debug and Analysis Reference Solution - Solution Brochure
Next-Generation DDR4 Test Challenges
System and memory designers implementing DDR4 are striving for innovations in performance,
density and power efficiency in their systems. Reliable measurements and analysis enable
market-changing innovations and rapid fault isolation by providing insight into actual system
behavior.
Using Keysight’s DDR4 functional/protocol debug and analysis solution
to address DDR4 test challenges
Keysight’s DDR4 functional/protocol debug and analysis reference solution is the industry’s
only functional/protocol validation, debug, analysis and bus level signal integrity insight
solution covering address/command and data for DDR4 systems operating at data rates up to
and including 4000 Mb/s.
Solution feature
Proven capture of DDR4 Read/
Write data at 4000 Mb/s
100 ps by 100 mV minimum eye
requirement at probe point
2.5 GHz trigger sequencer with
burst trigger option
Exclusive quad sample mode
(Option U4164A-02G)
Extensive memory analysis
software (B4661A) makes your job
easier
DIMM, SODIMM, universal
footprint, and BGA probing
Timing zoom
Benefit
Follow the signal flow on DDR4 memory systems to isolate issues
–– Memory write back issues, initialization issues, system crashes, and system abnormalities
–– Visibility to all Address, Command and Data (Address/Command up to 5000 Mb/s data rates)
Reliable capture on the smallest eye openings. No other logic analyzer can capture eyes this small
Capture sequential up to 2.5 GHz. Capture up to 32 sequential events using Keysight’s exclusive burst trigger.
Competition triggers at 750 MHz, which is inadequate for DDR/LPDDR above 1500 Mb/s
Maximum signal access at highest data rates from one probe point
Allows simultaneous capture of Read/Write data at two different thresholds at rates up to 4000 Mb/s from a single
probe load
Debug, improve performance, and validate protocol compliance
DDR2/3/4 decoder/transaction viewer
Functional protocol compliance analysis for DDR4
–– Post-process compliance violation analysis
–– Protocol compliance violation testing across speed changes
–– Click to jump to worst violation or to mark violations
–– Margin information on violations
–– Real-time compliance violation analysis triggers on violations to identify elusive DDR4 system violations
–– User-defined regression tests for any logic analyzer configuration on any bus
Performance overview and analysis
–– Powerful traffic overview for rapid navigation to areas of interest
–– Analyzes and displays Activate/Read/Write/Precharge (page open/ page close)
–– Memory access views include BA: Row vs. time to highlight hot spots for potential row hammer issues
–– Unique refresh rate view: rolling window of % of refresh
–– Improve system performance with detailed metrics and graphs
Bus level signal insight
–– Qualitative eye scans (up to hundreds of signals) using DDR eye scan
Ease-of-use to minimize set up and analysis time
–– DDR setup assistant: Simplifies state mode measurement setup to minutes
–– DDR configuration creator enables users to create custom mid-bus or BGA configurations in minutes using an
interactive graphical interface
Allows you to connect to any DDR4 system under test for functional compliance validation, debug, and bus level
signal integrity insight
Provides 256k high-resolution (12.5 GHz) timing measurements simultaneous with full memory depth state or timing
measurements from single probe point