HE83139 Datasheet, PDF (2/9 Pages) King blillion Electronics Co.,Ltd. – 8-BIT MICRO-CONTROLLER

KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE83139
HE80000 SERIES
C. Pin Description
Pin # Pin name I/O Function
Description
External fast clock input/output Mask Option setting:
78
77
FXI,
FXO
B,
O
pins are used to connect crystal
or RC to generate the
32.768KHz ~ 8MHz system
MO_FCK/SCKN= 00 : Slow Clock only
01 : Illegal
10：Dual Clock
clock.
11：Fast Clock only
MO_FOSCE= 0：Internal fast clock
1：External fast clock
External slow clock input/output
pins used to connect the
MO_FXTAL= 0：R,C OSC. for Fast Clock
1：Crystal OSC. for Fast Clock
81
SXI,
I, 32.768KHz crystal to generate ^{MO_SXTAL= 0：R,C OSC. for 32.768K Clock}
80
SXO O slow clock for system operation
1：Crystal OSC. for 32.768K Clock。
(slow mode), LCD display or Use OP1 and OP2 to switch among different
timer 1 clock source.
operation mode (NORMAL, SLOW, IDEL and
SLEEP). In Dual Clock mode, the main system clock
is still the Fast Clock. The 32768 Hz clock is for LCD
and Timer 1 only.
Active low and level trigger reset signal. User can
also set the mask option MO_PORE=1 to enable the
build-in Power-on reset circuit besides using the reset
pin.
76 RSTP_N I System reset signal
Watch Dog Timer can also be enabled/disabled by the
mask option,
MO_WDTE = 0：Disable Watch Dog Timer
= 1：Enable Watch Dog Timer
Please bond this pin to ground by a 0 ohm
79 TSTP_P I IC Test Pin
resistor to let it accessible when it’s necessary for
some testing.
91,92,
93,1
NC
No Connection Pin
Mask options setting:
83..
90
PRTD[7:0]
Bi-directional I/O port D. PRTD ^{MO_DPP [7:0] = 1：Push-pull output.}
B [7:2] also used as wake-up pin,
= 0：Open-drain output.
and PRTD [7:6] also used as _{Output must be “1” before reading whenever uses}
external interrupt pin.
them as input (Non tri-state structure).
Mask options setting:
MO_17PP [7:0] = 1：Push-pull output.
12..19 PRT17[7:0] B Bi-directional I/O port 17
= 0：Open-drain output.
Output must be “1” before reading whenever uses
them as input (Non tri-state structure).
11..4
52..59
COM[15:0]
O LCD COM Output
20..51 SEG[31:0] O LCD SEG Output
LCD common/segment driving pins.
LCD Data filled from 80H; please refer the LCD
RAM map.
61
LC2 B Charge Pump Switch 1
When LV3=VDD, the charge pump for LCD is turn off.
60
LC1 B Charge Pump Switch 2
The capacitor between LC1 and LC2 shall be
removed to reduce power consumption.
63
LV3
B Charge Pump V3
62
LV1
B Charge Pump V1
Refer to application circuit.
2
V1.0