HE83115 Datasheet, PDF (2/10 Pages) King blillion Electronics Co.,Ltd. – 8-BIT MICRO-CONTROLLER

KING BILLION ELECTRONICS CO., LTD
駿億電子股份有限公司
HE83115
HE80000 SERIES
D. Pin Description
Pin # Pin name I/O
Function
Description
External fast clock pin. Mask option setting：
43 FXI,
42 FXO
B, Connecting to crystal or RC _{MO_FCK/SCKN= 00：Slow Clock only}
O to generate 32.768 kHz ~
01：Illegal
8MHz frequency.
10：Dual Clock
11：Fast Clock only
MO_FOSCE = 0：Internal fast osc.
46 SXI,
45 SXO
External slow clock pin.
Connecting with 32768 Hz
= 1：External fast osc.
MO_FXTAL= 0：RC osc. for fast clock
I,
O
crystal or resistor as slow
clock and providing clock
source for LCD display,
= 1：X’tal osc. for fast clock
MO_SXTAL= 0：RC for 32768 Hz clock
= 1：X’tal for 32768 Hz clock
TIMER1, Time-Base and _{Use OP1 and OP2 to switch among different operation}
other internal blocks.
mode (NORMAL, SLOW, IDEL and SLEEP). In Dual
Clock mode, the main system clock is still the Fast
Clock. The 32768 Hz clock is for LCD and Timer 1
only.
Level trigger, active low. Except for using this pin, using
mask option (MO_PORE=1) could enable IC build-in
41 RSTP_N I System Reset.
power-on reset circuit.
Besides, MO_WDTE can set Watch Dog Timer：
MO_WDTE=0：Disable Watch Dog Timer
=1：Enable Watch Dog Timer
44 TSTP_P I Test Pin
Please bond this pin and add a test point on PCB for
debugging. Leave this pin floating is OK.
Mask options：
MO_CPP[3..0]=1 ~ Push-pull.
1..4 PRTC[3:0] B 4-pin bi-directional I/O port.
=0 ~ Open-drain.
Output must be “1” before reading whenever use them
48..
55
PRTD[7:0]
B
as input (No tri-state structure).
8-pin bi-directional I/O port.
PRTD[7..2] as wake-up pin.
PRTD[7..6] as external
interrupt pin.
Mask options：
MO_DPP[7..0]=1 ~ Push-pull.
=0 ~ Open-drain.
Output must be “1” before reading whenever use them
as input (No tri-state structure).
Mask options：
7..14
PRT14[7:0]/
SEG[19:12]
B/
O
8-pin bi-directional I/O port
that is shared with LCD
segment pin.
MO_LIO14[7..0]=1 ~ LCD Pin.
=0 ~ I/O Pin.
MO_14PP[7..0]=1 ~ Push-pull.
=0 ~ Open-drain.
Output must be “1” before reading whenever use them
as input (No tri-state structure).
27..
30
COM[3:0]
O
LCD COMmon Output
LCD Data filled from F0H, please refer the LCD RAM
15..
26
SEG[11:0]
O
LCD SEGment Output
map.
32 LC2
B Charge Pump Switch 2
Add one 0.1 µF capacitor between LC1 and LC2. Please refer
31 LC1
B Charge Pump Switch 1
the application circuit.
35 LV3
B Charge Pump V3
LV3< 9 Volts.
2
V3.3E