8T49N281_16 Datasheet, PDF (51/67 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N281 Datasheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs generate ECL/LVPECL compatible outputs.
Therefore, terminating resistors (DC current path to ground) or
current sources must be used for functionality. These outputs are
designed to drive 50 transmission lines. Matched impedance
techniques should be used to maximize operating frequency and
minimize signal distortion. Figure 10A and Figure 10B show two
different layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended that
the board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
3.3V
3.3V
R3
R4
125
125
3.3V
Z_o = 50
+
Z_o = 50
R1
84
_
R2
84
Input
Figure 10A. 3.3V LVPECL Output Termination
Figure 10B. 3.3V LVPECL Output Termination
©2016 Integrated Device Technology, Inc.
51
Revision 7, October 26, 2016