8T49N281_16 Datasheet, PDF (31/67 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N281 Datasheet
Table 6P. Interrupt Status Register Bit Field Locations and Descriptions
This register contain sticky’ bits for tracking the status of the various alarms. Whenever an alarm occurs, the appropriate Interrupt Status bit
will be set. The Interrupt Status bit will remain asserted even after the original alarm goes away. The Interrupt Status bits remain asserted until
explicitly cleared by a write of a ‘1’ to the bit over the serial port. This type of functionality is referred to as Read / Write-1-to-Clear (R/W1C).
Interrupt Status Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
0200
Rsvd
LOL_INT
Rsvd
HOLD_INT
Rsvd
Rsvd
LOS1_INT LOS0_INT
0201
Rsvd
0202
Rsvd
0203
Rsvd
Bit Field Name
LOL_INT
HOLD_INT
LOSm_INT
Rsvd
Field Type
R/W1C
R/W1C
R/W1C
R/W
Interrupt Status Register Block Field Descriptions
Default Value Description
Interrupt Status Bit for Loss-of-Lock on PLL:
0 = No Loss-of-Lock alarm flag on PLL has occurred since the last time this register
0b
bit was cleared
1 = At least one Loss-of-Lock alarm flag on PLL has occurred since the last time this
register bit was cleared
Interrupt Status Bit for Holdover on PLL:
0 = No Holdover alarm flag on PLL has occurred since the last time this register bit
0b
was cleared
1 = At least one Holdover alarm flag on PLL has occurred since the last time this
register bit was cleared
Interrupt Status Bit for Loss-of-Signal on Input Reference m:
0 = No Loss-of-Signal alarm flag on Input Reference m has occurred since the last
0b
time this register bit was cleared
1 = At least one Loss-of-Signal alarm flag on Input Reference m has occurred since
the last time this register bit was cleared
-
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 6Q. Output Phase Adjustment Status Register Bit Field Locations and Descriptions
Output Phase Adjustment Status Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
0204
PA_BUSY7 PA_BUSY6 PA_BUSY5 PA_BUSY4 PA_BUSY3 PA_BUSY2
D1
PA_BUSY1
D0
PA_BUSY0
Bit Field Name
PA_BUSYm
Output Phase Adjustment Status Register Block Field Descriptions
Field Type Default Value Description
Phase Adjustment Event Status for output Qm, nQm:
R/O
-
0 = No phase adjustment is currently in progress on output Qm, nQm
1 = Phase adjustment still in progress on output Qm, nQm. Do not initiate any new
phase adjustment at this time
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Revision 7, October 26, 2016