CT2-PI1LATD31C Datasheet, PDF (4/8 Pages) JDS Uniphase Corporation – OC-12 SFP Transceiver (Multirate,1310 nm and 1550 nm)

4
CT2 Electrical Pad Layout
20 VeeT
19 _TD-
18 TD+
17 _VeeT
16 VccT
15 VccR
14 _VeeR
13 RD+
12 _RD-
11 _VeeR
Top of Board
OC-12 SFP TRANSCEIVER
1
VeeT
2
Tx Fault
3
Tx Disable
4
MOD-DEF(2)
5
MOD-DEF(1)
6
MOD-DEF(0)
7
Rate Select
8
LOS
9
VeeR
10 _VeeR
Bottom of Board (As Viewed
through Top of Board)
Transceiver Pin Descriptions
Pin
TD
TDb
RD
RDb
Rate_select
TxDIS
LOS
Tx_fault
MOD_DEF(0)
MOD_DEF(1)
MOD_DEF(2)
VccR, VccT
VeeR, VeeT
Description
Un-clocked, multirate, differential serial bit stream (155 Mb/s to 622 Mb/s) used to drive the optical transmitter.
Internally AC coupled and terminated via internal 100 Ω differential impedence.
Differential received electrical signal capable of detecting 155 Mb/s to 622 Mb/s bit patterns.
The differential pair is internally biased and AC coupled. This signal requires 100 Ω external differential termination.
Internally monitored and available for future use. Can be customized for specific applications.
Transmitter Disable Input. A logic HIGH on this input pin disables the transmitter's laser so that there is no optical
output. If left open the transmitter will be disabled.
Loss of Signal (Open Collector). A logic HIGH on this output indicates an incoming signal level that is less than
-32 dBm but no greater than -38 dBm. LOS shall deassert (logic LOW) when a 3 dB (maximum), 0.5 dB (minimum)
hysteresis is obtained.
Transmitter fault (Open collector). A logic HIGH indicates that the transmitter is in a fault condition.
MOD_DEF(0) is internally grounded to indicate the presence of the module. Must be pulled-up on host board with
a 10 KΩ resistor.
MOD_DEF(1) is the clock of the 2 wire interface for module monitoring.
MOD_DEF(2) is the data line of the 2 wire interface for module monitoring.
Receiver, Transmitter power supply, respectively
Receiver, Transmitter ground, respectively. The chassis ground and circuit ground isolation is configurable.