CPC5903 Datasheet, PDF (9/15 Pages) IXYS Corporation – Bidirectionally Buffers I2C SDA Signal

INTEGRATED CIRCUITS DIVISION
dependent on the end product’s design criteria and the
operational characteristics of the CPC5903.
On Side A of the CPC5903, pull-ups chosen for
Fast-mode (up to 6mA) drivers can be used with no
loss of noise margin.
At the Side B outputs, OB and IOB, pull-up resistor
values should be chosen for Standard-mode 3mA
pull-up current or less when V_DDB < 4.5V. Additionally,
because V_IL at Side B is 0.2V_DDB , the pull-up resistor
on IOB must be large enough that the weakest driver
on the Side B bus can pull the voltage reliably below
0.2V_DDB . When V_DDB > 4.5V, the CPC5903 Side B
outputs will drive up to 6mA, and resistor pull-ups
chosen for up to 6mA can be used, provided all the
other devices on the bus have sufficient drive.
3.5 Pulse Propagation, Stretching and Delays
Due to glitch protection circuitry within the CPC5903
applying a pulse at the IOB input inherently involves
the use of the output driver at that I/O. Once an
asserted signal at IOB is determined to be valid, it is
stretched until it’s transmission through the optics has
been verified. This insures that there will be no extra
edges generated at either side due to optic delays. If a
Side B asserted-low pulse is long enough to be
accepted and passed to Side A, then the flip-flop at
Side B is set and remains set until the signal returns
through the optics from Side A. While the flip-flop is
set, IOB will output a voltage limited logic low, thereby
holding the bus at a logic low.
In operation, a valid asserted pulse of less than 80ns
applied at IOB appears at Side A after a delay largely
determined by the low-pass filter delay (t_FIL) and the
optics delay (t_{OPHL_BA}). After this initial delay the
Side A driver IOA is activated and a logic low is
asserted at time:
t_STARTA = t_FIL + t_{OPHL_BA}
That assertion is returned across the optics to Side B
after a delay largely determined by t_{OPHL_AB}. Upon
arriving at Side B, the flip-flop is cleared with the
incoming signal from Side A sustaining the IOB
voltage limited logic low. With the prior loss of the
asserted logic low by the external I²C device, and
because the IOB input does not accept it’s own output
low as valid, a deassertion is sent through the optics to
CPC5903
Side A, arriving at the Side A output after a delay
largely determined by t_{OPLH_BA} at time:
t_ENDA = t_FIL + t_{OPHL_BA} + t_{OPHL_AB} + t_{OPLH_BA}
Thus a valid Side B pulse having a width less than
80ns is stretched at Side A to a typical width of 125ns.
The duration of the pulse width output onto the Side A
bus is given by:
t_{PWA_min} = (t_{OPHL_AB} + t_{OPLH_BA})
When Side A is deasserted, the output rises at a slew
rate determined by the RC load on IOA, and passes
the logic threshold after time t_SLEWA. The deasserted
(logic HIGH) input propagates through the optics and
deasserts the Side B output after a delay largely
determined by t_{OPLH_AB}. Side B deassertion occurs at
time t_ENDB given by:
t_ENDB = t_ENDA + t_SLEWA + t_{OPLH_AB}
Consequently at Side B input, an applied pulse of less
than 80ns is stretched to:
t_{PWB_min} = t_FIL + t_{OPHL_BA} + t_{OPHL_AB} + t_{OPLH_BA} + t_SLEWA + t_{OPLH_AB}
which is typically 330ns. More importantly, only one
pulse is seen at both ports, with no extra or missing
clock or data edges, assuring bus integrity.
Pulses of width larger than approximately 80ns
applied to the Side B input do not utilize the flip-flop to
terminate the pulse, but do need to propagate to
Side A and then back to Side B when returning high
after being asserted low. The Side A pulse width is
given by the usual pulse width distortion relation:
t_{PWA_nom} = t_PULSE + t_{PLH_BA} - t_{PHL_BA}
which is typically t_PULSE + 75ns. Note that t_{PLH_BA} and
t_{PHL_BA} are observed at the external pins, and are
provided in the table, “Electrical Specifications” on
page 4. The pulse at Side B is asserted by an
external driver pulling low, and lasts for time t_PULSE. At
the end of the pulse, the rising edge passes through
the internal filter with delay t_FIL, then is applied to the
LED and received at Side A t_{OPLH_BA} later. After time
t_SLEWA the output at Side A crosses the logic high
threshold causing the Side A LED drive to deactivate,
which propagates the deasserted state back to Side B
with a delay of t_{OPLH_AB}.
R02
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