CPC5903 Datasheet, PDF (8/15 Pages) IXYS Corporation – Bidirectionally Buffers I2C SDA Signal

INTEGRATED CIRCUITS DIVISION
3 Functional Description
3.1 Introduction
The CPC5903 combines the features of multiple logic
optoisolators and an I²C bus repeater in a single 8-pin
package. It offers excellent isolation (3750V_rms) and
speed sufficient to support I²C Fast-mode at 400kbps.
It bidirectionally buffers the I²C data signal across the
isolation barrier, and unidirectionally buffers the clock
from Side A to Side B. If different supply voltage levels
are used at each side, then the part, in conjunction
with its external pull-up resistors, will perform logic
level translation for V_DD between 2.7V and 5.5V at
either side. Due to the unidirectional nature of the
clock buffer it is required that the bus master be
connected to Side A of the CPC5903.
Configured with one bidirectional channel and one
unidirectional channel, the CPC5903 is ideal for
systems that do not implement clock stretching or
have bus masters on the Side B bus. This provides a
savings in supply current compared with using a dual
bidirectional isolator, but at the cost of losing the ability
to implement a Side B bus master or clock-stretching
in the future.
Like available non-galvanically isolating I²C bus
repeaters, the CPC5903 has a full-drive side (Side A)
and a limited-drive side (Side B).
On Side B, IOB is a voltage-limited output driver with a
reduced logic low input voltage threshold (V_IL). An
internally set voltage limit prevents IOB from driving to
a V_OL level it will accept as a input logic low. This
guarantees the bidirectional buffer cannot drive itself
into a latched logic low condition, which would cause
I²C bus contention. IOB is specified with a minimum
V_OL-V_IL margin of 25mV at minimum V_DDB, and
exhibits a proportionately larger self-drive margin with
larger V_DDB.
IOA, the bidirectional buffer on Side A, is rated as a full
strength (6mA), FAST-mode driver over the full V_DDA
range with input thresholds specified as FAST-mode
compliant; thus the IOA output will drive the full 400pF
Fast-mode C_LOAD and is allowed to drive its own input
to a logic low.
CPC5903
3.2 Fast-mode Operation
Fast-mode operation of the CPC5903 bidirectional
interface on Side A is available over the full operational
range of the device. While Side B operation is
Standard-mode compliant over the full operational
range of the device, it is Fast-mode speed capable
whenever the bus loading is limited to 200pF. Full
Fast-mode compatible operation of the Side B bus is
available whenever V_DDB is 4.5V or greater.
3.3 Logic Input Thresholds and Output Levels
Because Side A is Fast-mode compliant, it’s inputs
IOA and IA have logic threshold levels and frequency
performance compliant with traditional I²C bus
interface devices. Additionally, the output capability of
IOA is Fast-mode compliant over the entire operational
range.
The output levels of OB and IOB are compatible with
traditional I²C bus interface devices, but are
voltage-limited. The input logic low threshold level of
IOB is configured lower than traditional I²C devices
and lower than it’s own output logic low level. This
eliminates the possibility of the IOB output driver
acquiring an IOB input logic low, which would result in
a latched logic low state.
Because Side B of the CPC5903 utilizes a modified
logic low threshold level, only one such device is
allowed on the Side B bus. Side A has no such
restriction as this side of the CPC5903 uses traditional
logic thresholds. This allows for cascaded isolation by
connecting the Side B of one CPC5903 to Side A of
the next.
Devices meeting the I²C specification are easily able
to drive the IOB input below the CPC5903’s lower V_IL
(0.2V_DDB) threshold at the Side B input, and will
correctly accept the Side B driven data, thereby
enabling Side B bidirectional communication.
3.4 Pull-Up Resistor Selection
Pull-up resistors are required on both sides of the
barrier. Selecting the value of the pull-up resistors is
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