CPC7701 Datasheet, PDF (8/11 Pages) IXYS Corporation – 16-Channel High Voltage Analog Switch with Integrated Bleed Resistors

INTEGRATED CIRCUITS DIVISION
2. Functional Description
The CPC7701 takes a serial stream of input data
along with a synchronous clock signal. As the clock
transits from low to high, the data at the input of each
shift register is shifted through from SR(n) to SR(n+1).
A high data bit, a “1,” represents an ON switch; a low
data bit, a “0,” represents an OFF switch. Data is input
and shifted through the internal shift register until all
sixteen shift register positions, SR0 through SR15, are
in the desired state.
D_IN: The data-in line presents data bits to the
CPC7701 to be shifted through the internal shift
register. The last bit into the shift register is the SW0
control bit.
CLK: The clock signal's rising edge is associated only
with shifting data into and through the shift register.
CL: The clear line overrides all other inputs. When CL
is high, the shift register is asynchronously cleared to
all 0s and all latches are set low, which causes all
output switches to be turned OFF immediately. When
CL is low, all output switches remain in whatever state
they are in, ON or OFF, in response to CLK, latch
inputs, and the LE signal.
LE: latch enable controls the state of the latches and
the state of the sixteen switches. If LE is high, then the
latches do not change states, but retain their most
recent status: either ON or OFF. With LE high, input
data and CLK have no effect on the state of the output
switches. If LE is low, then all latch outputs and their
switch states follow the inputs from the shift register.
LE is overridden by CL: no matter what state LE is in,
CL clears the latches. See “Truth Table” on page 9.
Note that holding LE active while clocking in new data
will cause the outputs to toggle with the shifting data.
D_OUT: The data-out pin is the output of SR15. After
sixteen clock pulses, the first bit of sixteen shifted input
data bits is output at SR15, and appears on D_OUT.
SW0 - SW15: The CPC7701 provides sixteen
high-voltage SPST output switches with a nominal
small signal on-resistance of 25. The two
connections of each switch are not polarity-sensitive.
As can be seen in “Block Diagram” on page 1,
integrated bleed resistors are provided to facilitate
charge dissipation for capacitive load applications.
CPC7701
V_PP and V_NN: Voltage inputs to the level shifters for
each switch channel that translate the voltage level of
the latch output signals to an appropriate level for the
voltages being switched.
The high-voltage output switches are turned on and off
in response to the data sent into the latches from the
shift register: data 0 turns a switch OFF, data 1 turns a
switch ON.
Two or more CPC7701 devices can be cascaded to
form an n-switch arrangement. The D_OUT pin of the
first is connected to the D_IN pin of the next in the
series. All devices are connected to the same clock
(CLK) signal. LE of all devices would normally be
connected, as would CL, but this is not necessary.
The first data bit applied to D_IN of the CPC7701,
whether it's a single device or several cascaded
devices, ripples through to the last switch output in line
after the application of a full clocking sequence of 16
clock pulses. Setting the serial I/O device to output the
most significant bit (MSB) first, results in the MSB
appearing on SW15 of the last device in line after a full
clocking sequence.
D_IN
CLK
D_IN
CLK
SW0
CPC7701
CL
CL
LE
LE
D_OUT
SW15
D_IN
CLK
CPC7701
CL
LE
D_OUT
SW0
SW15
D_IN
CLK
CPC7701
CL
LE
D_OUT
SW0
SW15
8
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