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CPC7701 Datasheet, PDF (6/11 Pages) IXYS Corporation – 16-Channel High Voltage Analog Switch with Integrated Bleed Resistors
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INTEGRATED CIRCUITS DIVISION
CPC7701
1.5.2 Logic Timing Characteristics
(Over recommended operating conditions unless otherwise noted.)
Parameter
Setup time before LE rises
Time width of LE
Clock delay time to Data Out
Time width of CL
Setup time, data to clock
Hold time, data from clock
Clock frequency
Clock rise and fall times
Turn-on time
Turn-off time
Symbol
Test Conditions
tSD
-
tWLE
VDD=3V
VDD=5V
tDO
VDD=3V
VDD=5V
tWCL
-
tsu
VDD=3V
VDD=5V
th
-
fCLK
50% duty cycle, fDATA= ½ fCLK, VDD=3V
50% duty cycle, fDATA= ½ fCLK, VDD=5V
tr , tf
-
ton
toff
VSW=VPP-10V, RL=10k
0°C
min max
150 -
56
-
12
-
10 100
5 45
55
-
21
-
7
-
2
-
-
8
-
20
-
50
-
5
+25°C
min typ max
150 -
-
56
-
-
12
-
-
10
-
100
5
-
45
55
-
-
-
21
-
-
7
-
2
-
-
-
-
8
-
-
20
-
-
50
-
-
5
70°C
Units
min max
150 -
56
-
12
-
10 100
5 45 ns
55
-
21
-
7
-
2
-
-
8
MHz
-
20
-
50 ns
-
5 s
1.5.3 Logic Timing Waveforms
DN-1
DN
DN+1
D
IN
50%
50%
LE
CLK
D
OUT
OFF
V
OUT
ON
50%
tsu
50%
t
WLE
tSD
50%
tDO
th
50%
toff
90%
50%
ton
10%
CL 50%
50%
t
WCL
6
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