EV6R11 Datasheet, PDF (2/7 Pages) IXYS Corporation – IX6R11 HALF BRIDGE DRIVER Evaluation Board

EV6R11 KIT
Schematic Diagram:
P1 pins P1-1 GND
P1-9 N/C
P1-2 HIN
P1-10 +VCL
P1
P1-3 LIN
P1-11 +VCL
P1-4 Vdd supply lineP1-12 LS (VCL GND)
P1-5 ENB active low P1-13 LS (VCL GND)
P1-6 PWM IN
P1-7 +5V for IXDB630
P1-8 external 630 drive
C1
10 UF 35V
C2
. 1UF
2 _{GN D}
U1
LM78L05 AC Z
C3
. 0 1U F
TP 5 ₁
TP 6
1
JP1
E NA S
R 4 10K
JP2
E NA T
R 5 10K
. 1UF
C1 1
+ C10
10 UF 35V
C13
. 1UF
13
EN B
C4
. 1UF
C5 = 27 pF for IXDP630
C5 = 22 pF for IXDP631
C6
C5
2 2PF
27p F (2 2pF )
Y1
XM/S M
R3
1K / 1M
1R
3S
5T
2 _ENAR
4 _ENAS
6
ENAT
U2
IXD P630/631
( Dead Timer )
7 _{OUTEN A}
8 _{RE SET (ac tiv e low)}
TP 1
TP 2
TU ¹³
TL ¹²
SU ¹⁵
SL ¹⁴
RU ¹⁷
RL ¹⁶
TP 3
TP 4
1
Q3
2N 700 0
1
3
Q4
2N 7000
1
3
R 13 jum pered
R 14 open
R 15 jum pered
R 16 open
12 _HIN
14
LI N
1 5 _{EN B}
14 _HIN
1 6 _{LI N}
R9
D1
10
U F-1007 DIC T
C7 +
C8
. 1UF
8
HGO
U3
HS ⁶
9
HS
R2
5. 1 1
DC BU S
TESTPO INT
C12
. 1UF
1
2
D3
Q2
IXF H7N 90Q
3
LGO ¹
2
LS
LS ¹⁶
Q2- S
TES TPO INT
HGO ⁸
U4
HS ⁷
HS ¹⁰
2
LG O
LS ¹
4
LS
LS ¹⁸
C9
. 1UF 1K V
Q1- D
TES TPO INT
2
R1
Q1
1
IXF H7N 90 Q
5. 1 1
3
D2
LS GN D
TES TPO I N T
Figure 3: EV6R11 PCB Schematic
Schematic Notes:
This is a demonstration PCB and has been designed for flexibility and ease of use. The
schematic shows all options but does not mean the PCB is configured as such when ordered. The
PCB will be loaded with either the IX6R11S3 16 pin SOIC package (U3) OR the IX6R11S6 18 pin
SOIC package with heat sink tab (U4). The free-wheeling diodes, D2 and D3, are also not included
but can be installed if IGBTs are used.
Ordering:
EV6R11S3
EV6R11S6
PCB with IX6R11S3 16 pin SOIC IC package
PCB with IX6R11S6 18 pin SOIC IC package with heat tab
2