CPC7592 Datasheet, PDF (15/19 Pages) Clare, Inc. – Line Card Access Switch

INTEGRATED CIRCUITS DIVISION
CPC7592
Forcing T_SD to a logic high disables the thermal
shutdown circuit and is therefore not recommended as
this could lead to device damage or destruction in the
presence of excessive tip or ring potentials.
State
Ringing
All-Off
Break-
Before-
Make
Talk
IN_RINGING
1
1
0
0
Break-Before-Make Ringing to Talk Transition Logic Sequence for all Versions
IN_TEST LATCH
0
0
0
X
T_SD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Z
-
Off
On
On
Off
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero current to Off
Off
On
Off
turn off.
0
0
SW4 has opened
Off
Off
Off
Off
0
0
Z
Close Break Switches
On
Off
Off
Off
2.4 Data Latch
The CPC7592 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch is via the input pins IN_RINGING and IN_TEST while
the output of the data latch are internal nodes used for
state control. When the LATCH enable control pin is at
a logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch state.
Whenever the LATCH enable control pin is at logic 1,
the data latch is active and data is locked. Subsequent
changes to the input controls IN_RINGING and IN_TEST
will not result in a change to the control logic or affect
the existing switch state.
The switches will remain in the state they were in
when the LATCH changes from logic 0 to logic 1 and
will not respond to changes in input as long as the
LATCH is at logic 1. However, neither the T_SD input
nor the T_SD output control functions are affected by
the latch function. Since internal thermal shutdown
control and external “All-off” control is not affected by
the state of the LATCH enable input, T_SD will override
state control.
2.5 T_SD Pin Description
The T_SD pin is a bi-directional I/O structure with an
internal pull-up current source with a nominal value of
16 A biased from V_DD. As an output, this pin
indicates the status of the thermal shutdown circuitry.
Typically, during normal operation, this pin will be
pulled up to V_DD but under fault conditions that create
excess thermal loading the CPC7592 will enter
thermal shutdown and a logic low will be output.
As an input, the T_SD pin is utilized to place the
CPC7592 into the “All-Off” state by simply pulling the
input low. For applications using low-voltage logic
devices (lower than V_DD), IXYS IC Division
recommends the use of an open-collector or an
open-drain type output to control T_SD. This avoids
sinking the T_SD pull up bias current to ground during
normal operation when the all-off state is not required.
In general, IXYS IC Division recommends all
applications use an open-collector or open-drain type
device to drive this pin.
Setting T_SD to a logic 1 or tying this pin to V_CC allows
switch control using the logic inputs. This setting,
however, also disables the thermal shutdown circuit
and is therefore not recommended. As a result the
T_SD pin has two recommended operating states when
it is used as an input control. A logic 0, which forces
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