CPC7691 Datasheet, PDF (10/16 Pages) Clare, Inc. – Line Card Access Switch

INTEGRATED CIRCUITS DIVISION
As can be seen in "Figure 1. CPC7691 Block Diagram” on
page 1 the T_SD control bypasses the latch, therefore
the T_SD control functions are independent of the latch.
On designs that do not wish to individually control the
LATCH pins of multiple-port cards it is possible to bus
many (or all) of the LATCH pins together to create a
single, board-level enable control. The weak internal
pull-up allows a fan out of up to 32 when the system’s
LATCH control driver has a logic low minimum sink
capability of 4mA.
2.4 T_SD Pin Description
The T_SD pin is a bidirectional I/O structure with an
internal pull-up current source biased from V_DD having
a nominal value of 16A.
As an output, this pin indicates the status of the
thermal shutdown circuitry. During normal operation
this pin will be pulled up to V_DD, but under fault
conditions that create excess thermal loading, the
CPC7691 will enter thermal shutdown, and a logic low
will be output at the T_SD pin.
As an input, T_SD is utilized to place the CPC7691 into
the “All-Off” state. This is accomplished by simply
pulling T_SD to a TTL input logic low level. When used
as an input, forcing a logic high condition at T_SD will
not override the thermal shutdown capability.
As discussed earlier the T_SD control bypasses the
latch so that neither the input nor the output control
functions are affected by the latch. Consequently,
because T_SD is independent of the latch, the internal
thermal shutdown function and the external “All-Off”
control features are not affected by the state of the
LATCH input.
For applications using low-voltage logic devices (lower
than V_DD), IXYS Integrated Circuits Division
recommends the use of an open-collector or an
open-drain type output to control T_SD. This avoids
sinking the T_SD pull-up bias current to ground during
normal operation when the All-Off state is not
required. In general, IXYS Integrated Circuits Division
recommends all applications use an open-collector or
open-drain type device to drive this pin.
CPC7691
2.5 Under Voltage Switch Lock Out Circuitry
2.5.1 Overview
Smart logic in the CPC7691 now provides for switch
state control during both power-up and power loss
transitions. An internal detector is used to evaluate the
V_DD supply to determine when to de-assert the under
voltage switch lock out circuitry with a rising V_DD and
when to assert the under voltage switch lock out
circuitry with a falling V_DD. Any time an unsatisfactory
low V_DD condition exists, the under voltage lock out
circuit overrides user switch control by blocking the
information at the external input pins, and conditioning
internal switch commands to the All-Off state. Upon
restoration of V_DD, the switches will remain in the
All-Off state until the LATCH input is pulled low.
The rising V_DD switch lock-out release threshold is
internally set to ensure all internal logic is properly
biased and functional before accepting external switch
commands at the inputs to control the switch states.
For a falling V_DD event, the lock-out threshold is set to
assure proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed.
To facilitate hot plug insertion and system power-up
state control, the LATCH pin has an integrated weak
pull-up sourced from the V_DD power rail that will hold a
non-driven LATCH pin at a logic high state. This
enables board designers to use the CPC7691 with
FPGAs or other devices that provide high impedance
outputs during power-up and logic configuration.
2.5.2 Hot Plug and power-up Design Considerations
There are six possible start-up scenarios that can
occur during power-up with T_SD  0. They are:
1. IN_RINGING defined at power-up & LATCH = 0
2. IN_RINGING defined at power-up & LATCH = 1
3. IN_RINGING defined at power-up & LATCH = Z
4. IN_RINGING not defined at power-up & LATCH = 0
5. IN_RINGING not defined at power-up & LATCH = 1
6. IN_RINGING not defined at power-up & LATCH = Z
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