IS61SF25616 Datasheet, PDF (9/16 Pages) Integrated Silicon Solution, Inc – 256K x 16, 256K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM

IS61SF25616
IS61SF25618
ISSI ^®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
8
8.5
10
12
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
fMAX⁽³⁾
Clock Frequency
— 100
— 90
— 66
— 66
MHz
tKC⁽³⁾
Cycle Time
10 —
11 —
15 —
15 —
ns
tKH
Clock High Time
4
—
4.5 —
4.5 —
4.5 —
ns
tKL⁽³⁾
Clock Low Time
4
—
4.5 —
4.5 —
4.5 —
ns
tKQ⁽³⁾
Clock Access Time
—
8
— 8.5
— 10
— 12
ns
tKQX⁽¹⁾
Clock High to Output Invalid
2
—
2
—
2
—
2
—
ns
tKQLZ^(1,2) Clock High to Output Low-Z
0
—
0
—
0
—
0
—
ns
tKQHZ^(1,2) Clock High to Output High-Z
2 3.5
2 3.5
2 3.5
2 3.5
ns
tOEQ⁽³⁾
Output Enable to Output Valid
— 3.5
— 3.5
— 3.5
—
5
ns
tOELZ^(1,2) Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
ns
tOEHZ^(1,2) Output Disable to Output High-Z —
3.5
— 3.5
— 3.5
— 3.5
ns
tAS⁽³⁾
Address Setup Time
2
—
2
—
2
—
4
—
ns
tSS⁽³⁾
Address Status Setup Time
2
—
2
—
2
—
4
—
ns
tWS⁽³⁾
Write Setup Time
2
—
2
—
2
—
4
—
ns
tCES⁽³⁾
Chip Enable Setup Time
2
—
2
—
2
—
4
—
ns
tAVS⁽³⁾
Address Advance Setup Time
2
—
2
—
2
—
4
—
ns
tAH⁽³⁾
Address Hold Time
0.5 —
0.5 —
0.5 —
1.5 —
ns
tSH⁽³⁾
Address Status Hold Time
0.5 —
0.5 —
0.5 —
1.5 —
ns
tWH⁽³⁾
Write Hold Time
0.5 —
0.5 —
0.5 —
1.5 —
ns
tCEH⁽³⁾
Chip Enable Hold Time
0.5 —
0.5 —
0.5 —
1.5 —
ns
tAVH⁽³⁾
Address Advance Hold Time
0.5 —
0.5 —
0.5 —
1.5 —
ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
04/17/01